公开(公告)号：US06668237B1

公开(公告)日：2003-12-23

申请号：US10052720

申请日：2002-01-17

申请人： Steven A. Guccione ,  Prasanna Sundararajan ,  Scott P. McMillan

发明人： Steven A. Guccione ,  Prasanna Sundararajan ,  Scott P. McMillan

IPC分类号： G01R2728

CPC分类号： G01R31/318516

摘要： Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

摘要翻译： 用于测试可编程逻辑器件（PLD）电路的方法和系统。 主机数据处理装置配置有运行时重配置编程接口，并且在主机装置上执行调用接口的方法的运行时重配置测试程序。 响应于从测试程序调用的编程接口的方法，PLD配置有第一配置比特流。 响应于从测试程序调用的编程接口的方法，从PLD读回状态数据。 测试程序还识别状态数据和预期结果数据之间的差异。

公开(公告)号：US06530071B1

公开(公告)日：2003-03-04

申请号：US09676298

申请日：2000-09-28

申请人： Steven A. Guccione ,  Prasanna Sundararajan

发明人： Steven A. Guccione ,  Prasanna Sundararajan

IPC分类号： G06F1750

CPC分类号： G06F11/142 ,  G06F17/5054

摘要： Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.

摘要翻译： 用于容许可编程逻辑器件（PLD）中的缺陷的方法和装置。 PLD包括多个可配置逻辑元件和互连资源，其中一个或多个可配置逻辑元件和互连资源具有电路缺陷。 执行适合PLD的运行时重新配置的设计程序。 设计程序包括指定电路设计的可执行代码，并生成在可编程逻辑器件上实现电路设计的配置位流。 设计程序还包括有选择地跳过可配置逻辑元件并互连包含缺陷的资源的代码。 在各种实施例中，可以响应于输入参数跳过单个可配置逻辑元件，整行或整列元素。

公开(公告)号：US06665766B1

公开(公告)日：2003-12-16

申请号：US09639513

申请日：2000-08-14

申请人： Steven A. Guccione ,  Prasanna Sundararajan

发明人： Steven A. Guccione ,  Prasanna Sundararajan

IPC分类号： G06F1314

CPC分类号： G06F17/5054

摘要： An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.

摘要翻译： 适用于可编程逻辑器件（PLD）的配置界面。 PLD包括多个配置引脚和实现用于从PLD读取数据和向PLD写入配置数据的读和写协议的电路。 PLD外部的寄存器连接到PLD的配置引脚，处理器连接到寄存器。 处理器上的每个可执行程序的第一组程序被配置为从寄存器读取和写入值。 第二组程序，每个可执行的处理器，提供一个应用程序编程接口，用于通过第一组例程从PLD配置和读回数据。 接口例程的分层结构有助于从软件控制的配置接口逐渐改变为作为硬件和软件组合的接口。

公开(公告)号：US06922665B1

公开(公告)日：2005-07-26

申请号：US09757404

申请日：2001-01-08

申请人： Steven A. Guccione ,  Scott P. McMillan ,  Brandon J. Blodget

发明人： Steven A. Guccione ,  Scott P. McMillan ,  Brandon J. Blodget

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F17/5022

摘要： A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate objects that represent configurable logic elements of the PLD. During simulation, events are generated based on changes in output signal states of the objects. Each event includes an input signal state and identifies an object to which the input signal is to be applied. Since configurable logic elements are simulated, for example, lookup tables, instead of logic gates, fewer events need to be generated and processed than in a conventional simulator. In another embodiment, the system supports an interface that allows tools to interface with the simulator in the same manner as the tools interface with a PLD.

摘要翻译： 一种用于在器件级模拟可编程逻辑器件（PLD）的电路设计的方法和系统。 用于配置PLD的相同配置数据用于生成表示PLD的可配置逻辑元素的对象。 在仿真期间，根据对象输出信号状态的变化生成事件。 每个事件包括输入信号状态，并且识别输入信号要被施加到的对象。 由于模拟可配置的逻辑元件，例如，查找表而不是逻辑门，需要比传统的模拟器更少的事件被生成和处理。 在另一个实施例中，系统支持允许工具以与工具与PLD接口相同的方式与模拟器进行接口的接口。

公开(公告)号：US06363519B1

公开(公告)日：2002-03-26

申请号：US09335422

申请日：1999-06-17

申请人： Delon Levi ,  Steven A. Guccione

发明人： Delon Levi ,  Steven A. Guccione

IPC分类号： G06F1750

CPC分类号： G06N3/126 ,  G06F17/5054

摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.

摘要翻译： 公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。 建立具有各组数据的多个数据结构。 从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。 然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。 根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。 在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。 多个配置比特流群可以通过网络并行演进。

公开(公告)号：US6144933A

公开(公告)日：2000-11-07

申请号：US315787

申请日：1999-05-20

申请人： Steven A. Guccione

发明人： Steven A. Guccione

IPC分类号： G01R31/3185 ,  G06F11/32 ,  G06F11/36 ,  G06F17/50 ,  G06F9/455 ,  G06F19/00

CPC分类号： G06F11/3664 ,  G01R31/318516 ,  G06F11/324 ,  G06F11/3636 ,  G06F17/5054

摘要： An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability. According to another aspect of the invention, data can be written into a programmable device using an interactive software tool and a hardware device designed to interface with the programmable device. The software tool can optionally access the hardware device via a network server, thereby enabling remote configuration of the programmable device.

摘要翻译： 提供了可用于在编程设备中报告配置数据（即，各种配置位的状态）以及探测和刺激编程设备中的电路的交互式图形软件工具。 可以显示配置数据的图形或文字表示。 当与具有可寻址触发器的可编程器件（例如Xilinx XC6200系列的器件）一起使用时，本发明的一个实施例可以改变配置的器件中的任何可寻址触发器的状态。 本发明的图形化工具优选地使用诸如Java的高级编程语言来实现，并具有图形点和点击用户界面，对硬件的远程访问以及符号调试能力。 根据本发明的另一方面，可以使用交互式软件工具和设计为与可编程设备接口的硬件设备将数据写入可编程设备。 软件工具可以选择性地通过网络服务器访问硬件设备，从而实现可编程设备的远程配置。

公开(公告)号：US06539532B1

公开(公告)日：2003-03-25

申请号：US09335437

申请日：1999-06-17

申请人： Delon Levi ,  Steven A. Guccione

发明人： Delon Levi ,  Steven A. Guccione

IPC分类号： G06F1750

CPC分类号： G06N3/126 ,  G06F17/5054

摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.

摘要翻译： 公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。 建立具有各组数据的多个数据结构。 从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。 然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。 根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。 在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。 多个配置比特流群可以通过网络并行演进。

公开(公告)号：US06351143B1

公开(公告)日：2002-02-26

申请号：US09882615

申请日：2001-06-15

申请人： Steven A. Guccione ,  Delon Levi ,  Daniel J. Downs

发明人： Steven A. Guccione ,  Delon Levi ,  Daniel J. Downs

IPC分类号： G11C1500

CPC分类号： G11C15/00

摘要： Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a “match” signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables. A processor connected to the PLD responds to new CAM entries by executing instructions that first translate the new CAM entries into configuration data and then employ the configuration data to reprogram the PLD.

摘要翻译： 描述了利用现代可编程逻辑器件的运行时可重构性来有效地实现内容寻址存储器（CAM）电路的系统和方法。 不是使用可配置逻辑来比较存储在触发器中的CAM条目，根据本发明的CAM使用可配置的逻辑来进行数据存储和比较。 根据本发明的一个实施例的CAM包括可编程逻辑设备上的多个可编程查找表，其被共同配置为响应于提供在一系列数据输入端上的数据而产生“匹配”信号。 配置数据确定CAM响应的特定模式，因此通过配置（或重新配置）一个或多个查找表来引入新的CAM条目。 连接到PLD的处理器通过执行首先将新的CAM条目转换成配置数据的指令来响应新的CAM条目，然后使用配置数据重新编程PLD。

公开(公告)号：US06216259B1

公开(公告)日：2001-04-10

申请号：US09168300

申请日：1998-10-07

申请人： Steven A. Guccione ,  Delon Levi

发明人： Steven A. Guccione ,  Delon Levi

IPC分类号： G06F1750

CPC分类号： G06F17/5054

摘要： A system and method for configuration of a programmable logic device using routing cores. A program executing on a processor includes instructions that select functions to be provided by the programmable logic device. The instructions invoke functions from a library of logic and router core generators to define logic cores and router cores to intercouple the logic cores. From the logic and router core definitions, the program utilizes a bit-stream library to generate programming bits. The programmable logic device is then loaded with the programming bits by the program.

摘要翻译： 一种使用路由核心配置可编程逻辑器件的系统和方法。 在处理器上执行的程序包括选择要由可编程逻辑器件提供的功能的指令。 该指令调用逻辑库和路由器核心发生器的函数，以定义逻辑核心和路由器核心来互连逻辑核心。 从逻辑和路由器核心定义，程序利用位流库生成编程位。 然后可编程逻辑器件通过程序加载编程位。

公开(公告)号：US5995744A

公开(公告)日：1999-11-30

申请号：US023334

申请日：1998-02-13

申请人： Steven A. Guccione

发明人： Steven A. Guccione

IPC分类号： G01R31/3185 ,  G06F11/32 ,  G06F11/36 ,  G06F17/50 ,  G06F15/177 ,  G06F19/00

CPC分类号： G06F11/3664 ,  G01R31/318516 ,  G06F11/324 ,  G06F11/3636 ,  G06F17/5054

摘要： An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability. According to another aspect of the invention, data can be written into a programmable device using an interactive software tool and a hardware device designed to interface with the programmable device. The software tool can optionally access the hardware device via a network server, thereby enabling remote configuration of the programmable device.

摘要翻译： 提供了可用于在编程设备中报告配置数据（即，各种配置位的状态）以及探测和刺激编程设备中的电路的交互式图形软件工具。 可以显示配置数据的图形或文字表示。 当与具有可寻址触发器的可编程器件（例如Xilinx XC6200系列的器件）一起使用时，本发明的一个实施例可以改变配置的器件中的任何可寻址触发器的状态。 本发明的图形化工具优选地使用诸如Java的高级编程语言来实现，并具有图形点和点击用户界面，对硬件的远程访问以及符号调试能力。 根据本发明的另一方面，可以使用交互式软件工具和设计为与可编程设备接口的硬件设备将数据写入可编程设备。 软件工具可以选择性地通过网络服务器访问硬件设备，从而实现可编程设备的远程配置。