Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

发明授权

US06671644B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 失效

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专利标题： Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection
申请号： US09930355

申请日： 2001-08-15
公开(公告)号： US06671644B2

公开(公告)日： 2003-12-30
发明人: Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
主分类号： G06F1100
IPC分类号： G06F1100

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

摘要：

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

公开/授权文献

US20030036869A1 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 公开/授权日：2003-02-20

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