To change the frequency of a video clock without adversely affecting a display quality. To lower the frequency of a video clock, following steps are executed, detecting an opportunity which causes the reduction of the frequency of the video clock; lowering the frequency of the video clock in a frequency range within which a circuit employing the video clock (for example, a PLL (Phase Lock Loop) circuit) can follow a change in the frequency; and iterating the step of lowering the frequency of the video clock until a predetermined frequency is attained. In addition, the following steps are also performed, detecting an opportunity which causes the reduction of the frequency of the video clock; lowering the frequency of the video clock to a predetermined frequency during a vertical blanking interval of a display device that employs the video clock; and maintaining the predetermined frequency of the video clock until change of the frequency is required. Furthermore, the following steps are performed, detecting an opportunity which causes the reduction of the frequency of the video clock; changing a display color on a screen of a display device to a color for which flickers are not outstanding; and lowering the frequency of the video clock.