发明授权
- 专利标题: Selective deposition process for allowing damascene-type Cu interconnect lines
- 专利标题(中): 选择性沉积工艺允许镶嵌型Cu互连线
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申请号: US09477821申请日: 2000-01-05
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公开(公告)号: US06689689B1公开(公告)日: 2004-02-10
- 发明人: Paul R. Besser , Darrell M. Erb , Sergey Lopatin
- 申请人: Paul R. Besser , Darrell M. Erb , Sergey Lopatin
- 主分类号: H01L2144
- IPC分类号: H01L2144
摘要:
The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
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