Selective deposition process for allowing damascene-type Cu interconnect lines
    1.
    发明授权
    Selective deposition process for allowing damascene-type Cu interconnect lines 有权
    选择性沉积工艺允许镶嵌型Cu互连线

    公开(公告)号:US06689689B1

    公开(公告)日:2004-02-10

    申请号:US09477821

    申请日:2000-01-05

    IPC分类号: H01L2144

    摘要: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.

    摘要翻译: 通过包括在金属化特征的平坦化的上表面上选择性地沉积至少一个具有至少一个合金元素的薄层的方法来增强例如铜的平坦化在线金属化图案(例如铜)的可靠性和电迁移阻力, 金属的特征,然后将至少一个薄层的至少一种合金元素的至少最少量均匀地扩散到特征的上表面下方的预定最小深度以实现与其的合金化。 金属化特征的合金化部分有利地减少了电迁移。 通过CMP,可以在扩散/合金化之后进行平面化,以去除至少一个薄层的任何剩余的升高,合金化或非合金化部分。 本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

    Selective deposition process for passivating top interface of damascene-type Cu interconnect lines
    2.
    发明授权
    Selective deposition process for passivating top interface of damascene-type Cu interconnect lines 有权
    选择性沉积工艺,用于钝化镶嵌型Cu互连线的顶部界面

    公开(公告)号:US06455425B1

    公开(公告)日:2002-09-24

    申请号:US09484412

    申请日:2000-01-18

    IPC分类号: H01L2144

    摘要: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.

    摘要翻译: 通过包括选择性地在金属化特征的平坦化的上表面上沉积至少一个薄层的方法来增强平面化的在线金属化图案(例如铜)的可靠性,电迁移阻力,粘附性和电接触电阻,所述至少一个薄层包括 用于所述特征金属的至少一种钝化元素,使所述至少一种钝化元素反应以化学还原存在于所述金属化特征的上表面处的任何有害的氧化物层,以及使所述至少一种钝化元件在所述上部 表面形成钝化的顶部界面。 钝化的顶部界面有利地表现出减少的电迁移和改善对具有较低的欧姆接触电阻的上覆金属化的附着。 通过CMP,可以在反应/扩散之后进行平面化以除去至少一个薄层的任何升高的,反应的和/或未反应的部分。 本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

    Process for alloying damascene-type Cu interconnect lines
    3.
    发明授权
    Process for alloying damascene-type Cu interconnect lines 有权
    合金镶嵌型Cu互连线的工艺

    公开(公告)号:US06444567B1

    公开(公告)日:2002-09-03

    申请号:US09477822

    申请日:2000-01-05

    IPC分类号: H01L214763

    CPC分类号: H01L21/76886 H01L21/76849

    摘要: The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.

    摘要翻译: 通过包括在金属化特征和电介质的平坦化上表面上的覆盖沉积的方法来增强平面化金属化图案(例如,铜)沉积在介电材料层的表面中的可靠性和电迁移电阻 层至少一个薄层,其包含用于特征金属的至少一个合金元素,然后均匀地扩散至少最小量的至少一个薄层,以在金属化特征的上表面下方最小深度以实现合金化 随之而来。 金属化特征的合金化部分有利地减少了电迁移。 通过CMP,可以在扩散/合金化之后进行平面化,以去除至少一个薄层的任何剩余的升高,合金化或非合金化部分。 本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

    Process for passivating top interface of damascene-type Cu interconnect lines
    6.
    发明授权
    Process for passivating top interface of damascene-type Cu interconnect lines 有权
    钝化金刚石型Cu互连线顶界面的工艺

    公开(公告)号:US06319819B1

    公开(公告)日:2001-11-20

    申请号:US09484439

    申请日:2000-01-18

    IPC分类号: H01L214763

    CPC分类号: H01L21/76886

    摘要: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized metallization patterns, e.g., of copper, in-laid in the exposed upper surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, exposed upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form passivated top interfaces. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.

    摘要翻译: 在介电材料层的暴露的上表面中嵌入的铜的平坦化金属化图案(例如铜)的可靠性,电迁移阻力,粘附性和电接触电阻通过包括在平坦化, 金属化特征和电介质层的暴露的上表面,至少一个薄层,其包含用于特征金属的至少一种钝化元素,使至少一种钝化元素反应以化学还原存在于上述表面的任何有害的氧化物层 金属化特征,并且将至少一种钝化元件扩散到上表面下方一段距离以形成钝化的顶部界面。 钝化的顶部界面有利地表现出减少的电迁移和改善对具有较低的欧姆接触电阻的上覆金属化的附着。 通过CMP,可以在反应/扩散之后进行平面化以除去至少一个薄层的任何升高的,反应的和/或未反应的部分。 本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

    Composite tantalum nitride/tantalum copper capping layer
    7.
    发明授权
    Composite tantalum nitride/tantalum copper capping layer 有权
    复合氮化钽/钽铜覆盖层

    公开(公告)号:US07157795B1

    公开(公告)日:2007-01-02

    申请号:US10934511

    申请日:2004-09-07

    IPC分类号: H01L23/48

    摘要: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.

    摘要翻译: 通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层,显着降低了铜互连的电迁移和应力迁移。 实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷,沉积厚度为的厚度为的二氧化钛层,然后沉积厚度为200埃的α-Ta层 Å至500Å。

    Copper interconnect with improved barrier layer
    8.
    发明授权
    Copper interconnect with improved barrier layer 有权
    铜互连具有改进的阻挡层

    公开(公告)号:US06727592B1

    公开(公告)日:2004-04-27

    申请号:US10079515

    申请日:2002-02-22

    IPC分类号: H01L2348

    摘要: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

    摘要翻译: Cu互连,例如 通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构,通过PVD沉积α-Ta的闪光层,厚度小于30埃 阻挡层,沉积种子层,然后用Cu填充开口。 实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

    Selective electroplating with direct contact chemical polishing
    9.
    发明授权
    Selective electroplating with direct contact chemical polishing 失效
    选择性电镀与直接接触化学抛光

    公开(公告)号:US06454916B1

    公开(公告)日:2002-09-24

    申请号:US09477810

    申请日:2000-01-05

    IPC分类号: C25D1700

    摘要: A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.

    摘要翻译: 沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。 扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。 电镀材料填充图案化到半导体晶片的衬底中的凹槽,但是由于扩散器的接触和旋转,防止了在半导体晶片的顶表面上形成很大程度。 由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上,所以化学机械抛光(CMP)平面化被显着地减少或完全消除。

    Chemically removable Cu CMP slurry abrasive
    10.
    发明授权
    Chemically removable Cu CMP slurry abrasive 有权
    化学去除Cu CMP浆料研磨剂

    公开(公告)号:US06169034A

    公开(公告)日:2001-01-02

    申请号:US09199352

    申请日:1998-11-25

    IPC分类号: H01L21461

    摘要: Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.

    摘要翻译: 在CMP期间对Cu金属化的磨损降低,并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。 实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化,并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸,磷酸,硼酸或氟硼酸除去残留的氧化镁颗粒 。