Invention Grant
US06693046B2 Method of manufacturing semiconductor device having multilevel wiring
有权
制造具有多层布线的半导体器件的方法
- Patent Title: Method of manufacturing semiconductor device having multilevel wiring
- Patent Title (中): 制造具有多层布线的半导体器件的方法
-
Application No.: US10410247Application Date: 2003-04-10
-
Publication No.: US06693046B2Publication Date: 2004-02-17
- Inventor: Yukio Takigawa , Shun-ichi Fukuyama
- Applicant: Yukio Takigawa , Shun-ichi Fukuyama
- Priority: JP2002-187802 20020627; JP2002-338294 20021121
- Main IPC: H01L2131
- IPC: H01L2131
![Method of manufacturing semiconductor device having multilevel wiring](/abs-image/US/2004/02/17/US06693046B2/abs.jpg.150x150.jpg)
Abstract:
A method of manufacturing a semiconductor device includes the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of the first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface. A semiconductor device manufacturing method which can suppress peel-off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided.
Public/Granted literature
- US20040002208A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING MULTILEVEL WIRING Public/Granted day:2004-01-01
Information query