Invention Grant
US06693046B2 Method of manufacturing semiconductor device having multilevel wiring 有权
制造具有多层布线的半导体器件的方法

  • Patent Title: Method of manufacturing semiconductor device having multilevel wiring
  • Patent Title (中): 制造具有多层布线的半导体器件的方法
  • Application No.: US10410247
    Application Date: 2003-04-10
  • Publication No.: US06693046B2
    Publication Date: 2004-02-17
  • Inventor: Yukio TakigawaShun-ichi Fukuyama
  • Applicant: Yukio TakigawaShun-ichi Fukuyama
  • Priority: JP2002-187802 20020627; JP2002-338294 20021121
  • Main IPC: H01L2131
  • IPC: H01L2131
Method of manufacturing semiconductor device having multilevel wiring
Abstract:
A method of manufacturing a semiconductor device includes the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of the first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface. A semiconductor device manufacturing method which can suppress peel-off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided.
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