Invention Grant
US06707318B2 Low power entry latch to interface static logic with dynamic logic
失效
低功率输入锁存器,用于将静态逻辑与动态逻辑相连接
- Patent Title: Low power entry latch to interface static logic with dynamic logic
- Patent Title (中): 低功率输入锁存器,用于将静态逻辑与动态逻辑相连接
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Application No.: US10107740Application Date: 2002-03-26
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Publication No.: US06707318B2Publication Date: 2004-03-16
- Inventor: Sudarshan Kumar , Shahram Jamshidi
- Applicant: Sudarshan Kumar , Shahram Jamshidi
- Main IPC: H03K19096
- IPC: H03K19096

Abstract:
An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.
Public/Granted literature
- US20030184344A1 Low power entry latch to interface static logic with dynamic logic Public/Granted day:2003-10-02
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