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    VENTILATOR SYSTEM AND METHOD THEREOF
    2.
    发明申请
    VENTILATOR SYSTEM AND METHOD THEREOF 有权

    公开(公告)号：US20210316103A1

    公开(公告)日：2021-10-14

    申请号：US16896467

    申请日：2020-06-09

    Applicant: Sudarshan Kumar Bhandari ,  Purnima Bhandari

    Inventor： Sudarshan Kumar Bhandari ,  Purnima Bhandari

    IPC: A61M16/08 ,  A61M16/00 ,  A61M16/10 ,  A61M16/20

    Abstract: A ventilator system including an oxygen delivery cylinder, an air delivery unit, connecting tubes, and a digital display unit. The system further includes a Y connector configured to mix air and oxygen, to form a gas and pass said gas towards an outlet of the system. A water manometer that is configured to monitor a pressure of the gas in the system and blow off the excess pressure of the gas. A solenoid valve that is configured to adjust an end respiratory pressure obtained from a breathing device connected to the outlet of the system. The pressure of the gas being instantly delivered to the breathing device is measured by water manometer from a dead space near the outlet, thereby enabling a dual monitoring of the gas pressure being delivered to the breathing device.

    Method and apparatus to limit current-change induced voltage changes in a microcircuit
    3.
    发明授权
    Method and apparatus to limit current-change induced voltage changes in a microcircuit 失效
    限制微电路中电流变化感应电压变化的方法和装置

    公开(公告)号：US07685451B2

    公开(公告)日：2010-03-23

    申请号：US10327441

    申请日：2002-12-20

    Applicant: James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

    Inventor： James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

    IPC: G06F1/26

    CPC classification number: G06F1/305

    Abstract: A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

    Abstract translation: 公开了一种用于补偿电流变化感应电压变化的方法和装置。 在一个实施例中，耦合到指令流水线的数字节流单元可以生成补偿电流信号，然后可以使虚拟负载消耗补偿电流。 在另一个实施例中，响应于时钟频率变化的计数器可产生斜坡电流信号，然后可以使虚拟负载消耗对应于斜坡电流信号的电流。

    Low power entry latch to interface static logic with dynamic logic
    4.
    发明授权
    Low power entry latch to interface static logic with dynamic logic 失效
    低功率输入锁存器，用于将静态逻辑与动态逻辑相连接

    公开(公告)号：US06707318B2

    公开(公告)日：2004-03-16

    申请号：US10107740

    申请日：2002-03-26

    Applicant: Sudarshan Kumar ,  Shahram Jamshidi

    Inventor： Sudarshan Kumar ,  Shahram Jamshidi

    IPC: H03K19096

    CPC classification number: H03K3/356173 ,  H03K3/012 ,  H03K19/0963

    Abstract: An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

    Abstract translation: 输入锁存器，用于响应于下拉网络处的输入静态信号在输出端口处提供动态信号，所述下拉网络根据输入的静态信号来有条件地排放内部节点，所述输入锁存器包括具有第一源的传输晶体管 /漏极连接到输出端口，第二个源极/漏极连接到上拉pMOSFET的栅极，其中只有在评估阶段下拉网络未导通时，上拉电阻pOSOSFET才会导通。

    Low power clock buffer having a reduced, clocked, pull-down transistor
    6.
    发明授权
    Low power clock buffer having a reduced, clocked, pull-down transistor 有权
    低功耗时钟缓冲器具有降低时钟的下拉晶体管

    公开(公告)号：US6124737A

    公开(公告)日：2000-09-26

    申请号：US345972

    申请日：1999-06-30

    Applicant: Jiann-Cherng James Lan ,  Sudarshan Kumar ,  Kamal J. Koshy

    Inventor： Jiann-Cherng James Lan ,  Sudarshan Kumar ,  Kamal J. Koshy

    IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0948

    CPC classification number: H03K19/0016 ,  H03K19/01855

    Abstract: A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.

    Abstract translation: 时钟缓冲器包括时钟上拉晶体管和时钟控制下拉晶体管。 时钟上拉晶体管具有耦合到输出线的漏极和耦合到时钟信号线的栅极。 时钟控制的下拉晶体管包括耦合到输出线的漏极，耦合到时钟信号线的栅极并具有宽度Y.该缓冲器还包括第一下拉晶体管，其具有耦合到时钟信号源的漏极 下拉晶体管，耦合到第一输入信号线的栅极，并且具有比Y大至少10％的宽度。与较传统的时钟缓冲器相比，该时钟缓冲器提供了降低的功耗。

    Fast static CMOS adder
    7.
    发明授权
    Fast static CMOS adder 失效

    公开(公告)号：US5579254A

    公开(公告)日：1996-11-26

    申请号：US471287

    申请日：1995-06-06

    Applicant: Sudarshan Kumar ,  Jashojiban Banik

    Inventor： Sudarshan Kumar ,  Jashojiban Banik

    IPC: G06F7/50 ,  G06F7/506 ,  G06F7/38

    CPC classification number: G06F7/506 ,  G06F7/507

    Abstract: An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.

    Low power content addressable memory
    8.
    发明授权
    Low power content addressable memory 有权

    公开(公告)号：US11017858B1

    公开(公告)日：2021-05-25

    申请号：US15390500

    申请日：2016-12-25

    Applicant: Sudarshan Kumar

    Inventor： Sudarshan Kumar

    IPC: G11C15/04

    Abstract: A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.

    Gate-clocked domino circuits with reduced leakage current
    9.
    发明授权
    Gate-clocked domino circuits with reduced leakage current 失效
    具有降低漏电流的门控多米诺骨牌电路

    公开(公告)号：US06952118B2

    公开(公告)日：2005-10-04

    申请号：US10324307

    申请日：2002-12-18

    Applicant: Shahram Jamshidi ,  Sudarshan Kumar

    Inventor： Shahram Jamshidi ,  Sudarshan Kumar

    IPC: H03K19/096

    CPC classification number: H03K19/0963

    Abstract: A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

    Abstract translation: 在非活动状态下具有减小的漏电流的门时多米诺骨牌电路，其中多米诺骨牌电路中的多米诺级在预充电路径中具有长通道长度的晶体管。 在非活动状态期间，多米诺骨牌阶段被置于评估状态并被排除。

    Low power precharge scheme for memory bit lines
    10.
    发明授权
    Low power precharge scheme for memory bit lines 有权
    用于存储位线的低功率预充电方案

    公开(公告)号：US06631093B2

    公开(公告)日：2003-10-07

    申请号：US09895361

    申请日：2001-06-29

    Applicant: Sudarshan Kumar ,  Jiann-Cherng Lan ,  Wenjie Jiang ,  Gaurav Mehta ,  Sadhana Madhyastha

    Inventor： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Wenjie Jiang ,  Gaurav Mehta ,  Sadhana Madhyastha

    IPC: G11C700

    CPC classification number: G11C7/12

    Abstract: A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

    Abstract translation: 低功耗存储器位线预充电方案。 存储器位线耦合到第一读取预充电器件。 第二写入预充电装置也耦合到存储器位线，并且仅在响应于存储器写入操作时被使能。 第一读取和第二写入预充电装置的尺寸使其组合的驱动强度足以在写操作之后的预充电期间对第一存储器位线进行预充电。

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