发明授权
US06707318B2 Low power entry latch to interface static logic with dynamic logic
失效
低功率输入锁存器，用于将静态逻辑与动态逻辑相连接
- 专利标题： Low power entry latch to interface static logic with dynamic logic
- 专利标题（中）： 低功率输入锁存器，用于将静态逻辑与动态逻辑相连接
-
申请号： US10107740申请日： 2002-03-26
-
公开(公告)号： US06707318B2公开(公告)日： 2004-03-16
- 发明人: Sudarshan Kumar , Shahram Jamshidi
- 申请人： Sudarshan Kumar , Shahram Jamshidi
- 主分类号： H03K19096
- IPC分类号： H03K19096
摘要：
An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.
公开/授权文献
信息查询
