Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.