公开(公告)号：US06707457B1

公开(公告)日：2004-03-16

申请号：US09409819

申请日：1999-09-30

申请人： Matthew Damian Bates

发明人： Matthew Damian Bates

IPC分类号： G06T100

CPC分类号： G06F9/30029 ,  G06F9/30032 ,  G06F9/3885 ,  G06T1/20 ,  G06T15/005

摘要： Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.

摘要翻译： 本发明的实施例包括实现改进的图形生成系统的新装置和技术。 这种改进优选通过实现与CPU，控制寄存器部分，像素FIFO阵列部分，像素处理逻辑部分和控制逻辑部分接口的接口逻辑部分来实现。 这些部分优选地被实现为CPU的内部架构的扩展。 CPU可以经由数据高速缓存和写入缓冲器部分附加到图形系统。 数据从系统内存中读取并放置在数据高速缓存中，以便对同一位置的后续访问只需访问缓存。 将系统存储器数据写入写入缓冲器，使得写入的数据可以排队并在适当的时间发送到主存储器。 显示刷新控制器还从系统存储器中读取数据，并将数据转换为信号以输出到显示器。