Invention Grant
- Patent Title: Digital memory circuit having a plurality of memory areas
- Patent Title (中): 具有多个存储区域的数字存储电路
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Application No.: US10266355Application Date: 2002-10-07
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Publication No.: US06711072B2Publication Date: 2004-03-23
- Inventor: Helmut Fischer , Johann Pfeiffer
- Applicant: Helmut Fischer , Johann Pfeiffer
- Priority: DE10149099 20011005
- Main IPC: G11C700
- IPC: G11C700

Abstract:
A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local data lines is associated with one of the memory areas and is connected to a two-wire master data line, common to all the memory areas, by a line circuit-breaker. To represent the binary value of data on a local data line, the wires are driven, to first and second logic potentials. Each line circuit-breaker contains switching devices which, if one of the two wires in the local data line is at the second logic potential, autonomously transfer the potential to the associated wire in the master data line, and, if one of the two wires in the master data line is at the second logic potential, autonomously transfer the potential to the associated wire in the local data line.
Public/Granted literature
- US20030067821A1 Digital memory circuit having a plurality of memory areas Public/Granted day:2003-04-10
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