发明授权
US06711648B1 Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal
失效
通过响应于列地址选通信号产生延迟的地址转换检测信号来增加动态存储器件中的数据带宽的方法和装置
- 专利标题: Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal
- 专利标题(中): 通过响应于列地址选通信号产生延迟的地址转换检测信号来增加动态存储器件中的数据带宽的方法和装置
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申请号: US08825311申请日: 1997-03-28
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公开(公告)号: US06711648B1公开(公告)日: 2004-03-23
- 发明人: Peter Poechmueller , Yohji Watanabe
- 申请人: Peter Poechmueller , Yohji Watanabe
- 主分类号: G06F1200
- IPC分类号: G06F1200
摘要:
The present invention includes a cost efficient method of substantially increasing the data bandwidth of a dynamic random access memory (DRAM) device initially configured to operate in an extended data output (EDO) mode, the EDO DRAM device including at least one storage cell, a column decoder, an internal read/write data bus and an off chip driver latch, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column addresses is placed on the internal read/write data bus in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device and further wherein output data is stored in the off chip driver latch in response to a transfer pulse. The method includes the steps of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on internal read/write data bus until after a delayed generation of the ATD pulse in response to the falling edge of a column address strobe (CAS) signal, such that a first pipeline stage is thereby substantially defined.
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