发明授权
US06711719B2 Method and apparatus for reducing power consumption in VLSI circuit designs
失效
用于降低VLSI电路设计中的功耗的方法和装置
- 专利标题： Method and apparatus for reducing power consumption in VLSI circuit designs
- 专利标题（中）： 用于降低VLSI电路设计中的功耗的方法和装置
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申请号： US09928573申请日： 2001-08-13
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公开(公告)号： US06711719B2公开(公告)日： 2004-03-23
- 发明人: John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
- 申请人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.