公开(公告)号：US06985004B2

公开(公告)日：2006-01-10

申请号：US09781369

申请日：2001-02-12

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K17/16

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

公开(公告)号：US06711719B2

公开(公告)日：2004-03-23

申请号：US09928573

申请日：2001-08-13

申请人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John Maxwell Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas Michael Lepsic ,  Patrick Edward Perry ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

摘要翻译： 在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。 然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。 因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离 源不需要传播。 由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。 因此，整体IC功耗降低。

公开(公告)号：US10375897B2

公开(公告)日：2019-08-13

申请号：US15480900

申请日：2017-04-06

申请人： Scott A Tetreault

发明人： Scott A Tetreault

IPC分类号： A47G33/00 ,  A01G5/04 ,  B42F1/00 ,  F21V21/088 ,  F21W121/04 ,  F21S4/10 ,  F21Y115/10

摘要： The present embodiments relate to an illuminated wreath card holder comprising a wreath form, decorative material configured to create a wreath on the form, and a plurality of ornamental clamp assemblies that are attached to the wreath form and configured to releasably secure, display, and illuminate greeting cards on the wreath. Each ornamental clamp assembly comprises at least one ornamental cover, at least one clip, and at least one light that is positioned between the ornamental cover and the clip. When viewed from the front, the light is hidden behind the ornamental cover and casts a glow up onto the greeting card. The ornamental cover may be star-shaped and have a return flange at its back to which the light and clip are attached. The illuminated wreath card holder may have a power source and be packed in kit form.

公开(公告)号：US07469395B2

公开(公告)日：2008-12-23

申请号：US11952544

申请日：2007-12-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

公开(公告)号：US06246254B1

公开(公告)日：2001-06-12

申请号：US09455969

申请日：1999-12-06

申请人： Charles N. Choukalos ,  Alvar A. Dean ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： Charles N. Choukalos ,  Alvar A. Dean ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K19007

CPC分类号： G06F21/76 ,  G06F21/71 ,  G06F2221/2137

摘要： A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

摘要翻译： 一种用于防止专用集成电路（ASIC）的非法复制的方法。 ASIC由包括用于禁用ASIC的定时器电路的网络列表定义。 定时器电路包括分布在ASIC的不同芯中的多个级，以阻止电路的检测和去除。 定时器在设置为允许对ASIC设计进行评估的时间段之后超时。 在超时期后，ASIC设计的进一步使用受到阻碍。

公开(公告)号：US20180293916A1

公开(公告)日：2018-10-11

申请号：US15480900

申请日：2017-04-06

申请人： Scott A. Tetreault

发明人： Scott A. Tetreault

IPC分类号： G09F1/10 ,  A41G1/00 ,  A47F7/14 ,  A01G5/04

CPC分类号： A01G5/04 ,  B42F1/006 ,  F21S4/10 ,  F21V21/088 ,  F21W2121/04 ,  F21Y2115/10

摘要： The present embodiments relate to an illuminated wreath card holder comprising a wreath form, decorative material configured to create a wreath on the form, and a plurality of ornamental clamp assemblies that are attached to the wreath form and configured to releasably secure, display, and illuminate greeting cards on the wreath. Each ornamental clamp assembly comprises at least one ornamental cover, at least one clip, and at least one light that is positioned between the ornamental cover and the clip. When viewed from the front, the light is hidden behind the ornamental cover and casts a glow up onto the greeting card. The ornamental cover may be star-shaped and have a return flange at its back to which the light and clip are attached. The illuminated wreath card holder may have a power source and be packed in kit form.

公开(公告)号：US07346875B2

公开(公告)日：2008-03-18

申请号：US11176712

申请日：2005-07-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

摘要翻译： 电气布线结构及其设计方法。 该方法识别具有第一线和第二线的至少一个线对。 第二根线已经是三态的，也可以是三态的。 线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。 或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。 第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

公开(公告)号：US06970814B1

公开(公告)日：2005-11-29

申请号：US09539020

申请日：2000-03-30

申请人： Carl L. Ashley ,  Charles N. Choukalos ,  Scott A. Tetreault

发明人： Carl L. Ashley ,  Charles N. Choukalos ,  Scott A. Tetreault

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F19/00 ,  G06Q50/00

CPC分类号： G06F17/5022 ,  G06F2217/66

摘要： A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

摘要翻译： 一种用于模拟电路的方法和结构，包括从客户站点将初始存储器状态和初始输入信号输入到主机站内的核心逻辑，利用主站点和通过广域网连接的客户站点模拟电路（ 其中主机站点包含核心逻辑，客户站点包含客户逻辑，核心逻辑和形成电路的客户逻辑），将测试输出信号与期望的输出信号进行比较，并改变客户逻辑，直到测试输出信号一致 具有所需的输出信号。

公开(公告)号：US06792582B1

公开(公告)日：2004-09-14

申请号：US09713829

申请日：2000-11-15

申请人： John M Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  David E. Lackey ,  Thomas M. Lepsic ,  Susan K. Lichtensteiger ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  David E. Lackey ,  Thomas M. Lepsic ,  Susan K. Lichtensteiger ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F17/5068

摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

摘要翻译： 公开了电压岛的逻辑和物理结构。 半导体芯片设计被划分为“箱”，这是设计的区域。 以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。 每个仓可以被认为是电压岛。 设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率 如果将电路放置在具有较低电压的箱中，则减小。 还可以改变箱子的大小和位置。 通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。 本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。

公开(公告)号：US06535016B2

公开(公告)日：2003-03-18

申请号：US09852784

申请日：2001-05-11

申请人： Charles N. Choukalos ,  Alvar A. Dean ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： Charles N. Choukalos ,  Alvar A. Dean ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K1900

CPC分类号： G06F21/76 ,  G06F21/71 ,  G06F2221/2137

摘要： A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

摘要翻译： 一种用于防止专用集成电路（ASIC）的非法复制的方法。 ASIC由包括用于禁用ASIC的定时器电路的网络列表定义。 定时器电路包括分布在ASIC的不同芯中的多个级，以阻止电路的检测和去除。 定时器在设置为允许对ASIC设计进行评估的时间段之后超时。 在超时期后，ASIC设计的进一步使用受到阻碍。