发明授权
US06717789B2 Power supply rejection circuit for capacitively-stored reference voltages 失效
用于电容性存储的参考电压的电源抑制电路

  • 专利标题: Power supply rejection circuit for capacitively-stored reference voltages
  • 专利标题(中): 用于电容性存储的参考电压的电源抑制电路
  • 申请号: US10008899
    申请日: 2001-12-05
  • 公开(公告)号: US06717789B2
    公开(公告)日: 2004-04-06
  • 发明人: Perry A. HolmanJason M. Chilcote
  • 申请人: Perry A. HolmanJason M. Chilcote
  • 主分类号: H02H322
  • IPC分类号: H02H322
Power supply rejection circuit for capacitively-stored reference voltages
摘要:
A power supply rejection circuit and method thereof for capacitively-stored reference voltages is disclosed. The power supply rejection circuit generally comprises a comparison circuit for comparing a signal associated with a power supply such as, for example, a Wheatstone bridge configuration, to a stored reference voltage, such that the comparison circuit includes at least one existing capacitor therein. At least one additional capacitor can be then coupled to the comparison circuit, such that the additional capacitor creates a capacitively-coupled voltage divider. This capacitively-coupled voltage divider negates the first order effects of power supply noise in the system. This effect significantly reduces the effect of power supply noise and improves signal jitter associated with the comparison circuit during a comparison of the signal to the stored reference voltage utilizing the comparison circuit.
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