发明授权
US06724476B1 Low defect metrology approach on clean track using integrated metrology
失效
使用综合计量的清洁轨道的低缺陷计量方法
- 专利标题: Low defect metrology approach on clean track using integrated metrology
- 专利标题(中): 使用综合计量的清洁轨道的低缺陷计量方法
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申请号: US10261756申请日: 2002-10-01
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公开(公告)号: US06724476B1公开(公告)日: 2004-04-20
- 发明人: Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
- 申请人: Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
- 主分类号: G01N2100
- IPC分类号: G01N2100
摘要:
One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.
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