发明授权
US06725343B2 System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
有权
用于在多处理器系统中生成高速缓存一致目录条目和纠错码的系统和方法
- 专利标题: System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
- 专利标题(中): 用于在多处理器系统中生成高速缓存一致目录条目和纠错码的系统和方法
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申请号: US09972477申请日: 2001-10-05
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公开(公告)号: US06725343B2公开(公告)日: 2004-04-20
- 发明人: Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
- 申请人: Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
- 主分类号: G06F1208
- IPC分类号: G06F1208
摘要:
Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory. When the cache memory system of the home node stores an exclusive copy of the particular memory line, the logic responds to the request by sending the copy of the particular memory line retrieved from the cache memory system and a predefined null directory entry value, and thus does not retrieve the memory line and its directory entry from the main memory of the home node.
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