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    Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system
    2.
    发明授权
    Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system 失效
    缓存一致性协议引擎系统和方法，用于在多处理器系统中的交织时间段期间处理不同地址子集中的存储器事务

    公开(公告)号：US06622217B2

    公开(公告)日：2003-09-16

    申请号：US09878983

    申请日：2001-06-11

    申请人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J Stets, Jr. ,  Andreas Nowatzyk

    发明人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J Stets, Jr. ,  Andreas Nowatzyk

    IPC分类号： G06F1200

    CPC分类号： G06F12/0828 ,  G06F2212/621

    摘要： The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.

    摘要翻译： 本发明一般涉及在多处理器计算机系统中使用的协议引擎。 实现高速缓存一致性协议的协议引擎包​​括时钟信号发生器，用于产生表示交织的偶数时钟周期和奇数时钟周期的信号，存储事务状态阵列，用于存储条目，每个表示各自的存储器事务的状态，以及处理 逻辑。 存储器事务被分为偶数和奇数事务，其状态存储在存储器事务状态数组中的不同的条目集合中。 处理逻辑具有交织电路，用于在甚至时钟周期期间处理偶数存储器事务并且用于在奇数时钟周期期间处理奇数存储器事务。

    Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
    3.
    发明授权
    Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants 有权
    多处理器高速缓存一致性系统和方法，其中处理器节点和输入/输出节点是相等的参与者

    公开(公告)号：US06925537B2

    公开(公告)日：2005-08-02

    申请号：US10698130

    申请日：2003-10-31

    申请人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr.

    发明人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr.

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0817 ,  G06F2212/621

    摘要： A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

    摘要翻译： 计算机系统具有多个处理器节点和多个输入/输出节点。 每个处理器节点包括多个处理器核心，到本地存储器系统的接口和实现预定义高速缓存一致性协议的协议引擎。 每个处理器核心具有用于缓存存储器信息线的相关联的存储器缓存。 每个输入/输出节点不包括处理器内核，用于与输入/输出总线或输入/输出设备进行接口的输入/输出接口，用于缓存存储器信息线的存储器缓存和到本地存储器子系统的接口。 每个处理器节点和输入/输出节点的本地存储器子系统存储多个存储器信息线。 每个处理器节点和输入/输出节点的协议引擎实现相同的预定义缓存一致性协议。

    System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
    4.
    发明授权
    System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system 有权
    用于在多处理器系统中生成高速缓存一致目录条目和纠错码的系统和方法

    公开(公告)号：US06725343B2

    公开(公告)日：2004-04-20

    申请号：US09972477

    申请日：2001-10-05

    申请人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    发明人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk

    IPC分类号： G06F1208

    CPC分类号： G06F12/0817 ,  G06F11/1064 ,  G06F11/1666 ,  G06F2212/2542

    摘要： Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory. When the cache memory system of the home node stores an exclusive copy of the particular memory line, the logic responds to the request by sending the copy of the particular memory line retrieved from the cache memory system and a predefined null directory entry value, and thus does not retrieve the memory line and its directory entry from the main memory of the home node.

    摘要翻译： 多处理器计算机系统的每个节点包括主存储器，高速缓冲存储器系统和逻辑。 主存储器存储数据的存储线。 每个存储器线的目录条目指示对应的存储器行的副本是否存储在另一个节点的高速缓存存储器系统中。 高速缓冲存储器系统存储指示每个存储器线的高速缓存副本是否是专用副本​​的存储器行的副本和高速缓存状态信息。 每个相应节点的逻辑被配置为响应特定存储器线及其对应的目录条目的事务请求，其中相应节点是特定存储器的归属节点。 当家庭节点的高速缓冲存储器系统存储特定存储器线的专用副本时，逻辑通过发送从高速缓冲存储器系统检索的特定存储器线的副本和预定义的空目录条目值来响应该请求，因此 不从主节点的主存储器检索内存条及其目录条目。

    System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
    5.
    发明授权
    System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system 有权
    用于在共享内存多处理器系统中缓存无效请求的有限扇出菊花链的系统和方法

    公开(公告)号：US07389389B2

    公开(公告)日：2008-06-17

    申请号：US10672960

    申请日：2003-09-26

    申请人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Robert J. Stets, Jr. ,  Mosur K. Ravishankar ,  Andreas Nowatzyk

    发明人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Robert J. Stets, Jr. ,  Mosur K. Ravishankar ,  Andreas Nowatzyk

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F7/00 ,  G06F15/16

    CPC分类号： G06F12/0826 ,  G06F2212/621 ,  Y10S707/99952

    摘要： A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.

    摘要翻译： 协议引擎用于具有多个节点的计算机系统的每个节点。 每个节点包括存储信息存储线，目录和存储器高速缓存的本地存储器子系统的接口。 目录包括与存储在本地存储器子系统中的信息的存储器线相关联的条目。 目录条目包括用于识别可能缓存信息的存储器线的共享者节点的标识字段。 识别字段在识别字段内的关联位置具有多个位。 识别字段的每个相应位与一个或多个节点相关联。 协议引擎还将存储线被高速缓存的标识字段中的每一位设置在相关联的节点中的至少一个中。 响应于对存储器线路的独占所有权的请求，协议引擎将初始无效请求发送到与存储器线相关联的目录条目的标识字段中与设置位相关联的不超过第一预定数量的节点。

    Scalable multiprocessor system and cache coherence method
    8.
    发明授权
    Scalable multiprocessor system and cache coherence method 失效
    可扩展的多处理器系统和缓存一致性方法

    公开(公告)号：US06751710B2

    公开(公告)日：2004-06-15

    申请号：US09878982

    申请日：2001-06-11

    申请人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr. ,  Daniel J. Scales

    发明人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr. ,  Daniel J. Scales

    IPC分类号： G06F1200

    CPC分类号： G06F12/0826 ,  G06F12/0828 ,  G06F2212/621

    摘要： The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.

    摘要翻译： 本发明一般涉及多处理器计算机系统，特别涉及使用有效的高速缓存一致性逻辑和方法来设计为高度可扩展的多处理器系统。 更具体地说，本发明是一种包括多个处理器节点的系统和方法，所述多个处理器节点被配置为执行避免使用否定确认消息（NAK）的高速缓存一致性协议以及对底层事务 - 消息互联/网络和服务的排序要求 只有一次访问家庭节点的3跳交易。