发明授权
- 专利标题： Fractional-frequency-modulation PLL synthesizer that suppresses spurious signals
- 专利标题（中）： 抑制杂散信号的分频调频PLL合成器
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申请号： US10283119申请日： 2002-10-30
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公开(公告)号： US06734739B2公开(公告)日： 2004-05-11
- 发明人: Tadashi Kawahara
- 申请人： Tadashi Kawahara
- 优先权： JP2002-161466 20020603
- 主分类号： H03L7089
- IPC分类号： H03L7089
摘要：
The phase comparator in a phase locked loop synthesizer has a identical first and second transmission gates connected to a front row and a back row of 2N−1 gate delay elements, respectively. Third and fourth transmission gates are permanently set to an ON setting. The first transmission gate and NAND gates operate as a gate delay element when a COUNT signal is at a low logical level and operate as a ring oscillator when the COUNT signal is at a high logical level.