发明授权
US06737748B2 Stacked via with specially designed landing pad for integrated semiconductor structures
有权
通过专门设计的集成半导体结构的着陆垫进行堆叠
- 专利标题: Stacked via with specially designed landing pad for integrated semiconductor structures
- 专利标题(中): 通过专门设计的集成半导体结构的着陆垫进行堆叠
-
申请号: US10082554申请日: 2002-02-25
-
公开(公告)号: US06737748B2公开(公告)日: 2004-05-18
- 发明人: Lothar Bauch , Thomas Zell , Matthias Uwe Lehr , Albrecht Kieslich
- 申请人: Lothar Bauch , Thomas Zell , Matthias Uwe Lehr , Albrecht Kieslich
- 优先权: DE19939852 19990823
- 主分类号: H01L2348
- IPC分类号: H01L2348
摘要:
In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.
公开/授权文献
信息查询