公开(公告)号：US06737748B2

公开(公告)日：2004-05-18

申请号：US10082554

申请日：2002-02-25

申请人： Lothar Bauch ,  Thomas Zell ,  Matthias Uwe Lehr ,  Albrecht Kieslich

发明人： Lothar Bauch ,  Thomas Zell ,  Matthias Uwe Lehr ,  Albrecht Kieslich

IPC分类号： H01L2348

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

摘要翻译： 在堆叠过孔的制造中，引入了称为着陆焊盘的金属岛，用于在彼此上下布置的通孔之间的接触连接的目的。 由于线路缩短效应，金属岛在很大程度上突出超出通孔。 布置在一个彼此上下的层中的通孔相对于彼此横向偏移。 本发明的着陆垫被配置为在通孔之间运行的互连。 由于对较长轨道不那么关键的线路缩短效应，互连端部设置的接触区域不必被选择为与常规金属岛的方形接触面积一样大，因此可以容纳到 节省电路布局上的更多空间以实现小型化。 这种半导体结构的收缩率增加。

公开(公告)号：US06559547B1

公开(公告)日：2003-05-06

申请号：US09663569

申请日：2000-09-15

申请人： Matthias Uwe Lehr ,  Albrecht Kieslich ,  Peter Thieme ,  Lars Voland

发明人： Matthias Uwe Lehr ,  Albrecht Kieslich ,  Peter Thieme ,  Lars Voland

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L21/31053 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

摘要翻译： 半导体结构具有由金属化层和电介质层形成的层结构。 金属化层被图案化并具有接触区域。 电介质层由可沉积材料构成并覆盖金属化层。 接触区域由许多连续的单独结构形成，这些结构非常窄，使得可沉积材料在单个结构上不形成平行于金属化层延伸的任何区域。 连续的单独结构的网格形成接触区域，其导致电介质层的高度特别低，因此易于平坦化。

公开(公告)号：US20050124124A1

公开(公告)日：2005-06-09

申请号：US10995677

申请日：2004-11-23

申请人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

发明人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

IPC分类号： H01L27/108 ,  H01L21/265 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

公开(公告)号：US20050032324A1

公开(公告)日：2005-02-10

申请号：US10886053

申请日：2004-07-08

申请人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

发明人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/10867

摘要： A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

摘要翻译： 一种用于制造沟槽结构的方法，特别是具有绝缘套环的沟槽电容器，其通过埋入触点电连接到一侧的衬底。 制造包括例如使用具有相应的掩模开口的硬掩模在衬底中提供沟槽; 提供至少部分沟槽填充; 在所得结构上提供衬垫; 将杂质离子倾斜地注入到衬垫上，以改变衬垫的注入部分区域的蚀刻性能; 通过第一蚀刻选择性地去除衬垫的注入部分区域，用于从衬垫的互补部分区域形成衬垫掩模，其部分地掩盖沟槽填充物的顶侧; 使用所述衬垫掩模通过第二蚀刻去除所述沟槽填充的一部分; 并更换去除的沟槽填充部分。

公开(公告)号：US07217610B2

公开(公告)日：2007-05-15

申请号：US10485308

申请日：2002-07-30

申请人： Werner Graf ,  Albrecht Kieslich

发明人： Werner Graf ,  Albrecht Kieslich

IPC分类号： H01L21/8238 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

摘要： A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

摘要翻译： 公开了用于在半导体衬底中集成用于存储器和逻辑应用的场效应晶体管的方法。 栅极电介质和半导体层沉积在逻辑区域和存储区域中的整个区域上。 从这些层，形成存储区域中的栅电极，注入源区和漏区，并且用绝缘材料以平坦化方式覆盖存储区。 之后，栅极电极由逻辑区域中的半导体层和栅极电介质形成。

公开(公告)号：US07189614B2

公开(公告)日：2007-03-13

申请号：US10886053

申请日：2004-07-08

申请人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

发明人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

IPC分类号： H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/10867

摘要： A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

摘要翻译： 一种用于制造沟槽结构的方法，特别是具有绝缘套环的沟槽电容器，其通过埋入触点电连接到一侧的衬底。 制造包括例如使用具有相应的掩模开口的硬掩模在衬底中提供沟槽; 提供至少部分沟槽填充; 在所得结构上提供衬垫; 将杂质离子倾斜地注入到衬垫上，以改变衬垫的注入部分区域的蚀刻性能; 通过第一蚀刻选择性地去除衬垫的注入部分区域，用于从衬垫的互补部分区域形成衬垫掩模，其部分地掩盖沟槽填充物的顶侧; 使用所述衬垫掩模通过第二蚀刻去除所述沟槽填充的一部分; 并更换去除的沟槽填充部分。

公开(公告)号：US06638814B1

公开(公告)日：2003-10-28

申请号：US10031743

申请日：2002-01-23

申请人： Albrecht Kieslich ,  Klaus Feldner ,  Herbert Benzinger

发明人： Albrecht Kieslich ,  Klaus Feldner ,  Herbert Benzinger

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/10829

摘要： A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件具有带存储电容器的第一区域和具有由绝缘体包围的至少一个阱的第二区域。 该方法通过在第一区域中形成沟槽和在第二区域中形成至少一个沟槽而形成存储电容器和绝缘体，并且沟槽具有至少2μm的深度。 处理第一区域中的沟槽以提供由电介质隔开的第一和第二电极以形成电容器，并且第二区域中的每个沟槽提供围绕第二区域中的任何孔的绝缘体。

公开(公告)号：US07259060B2

公开(公告)日：2007-08-21

申请号：US10995677

申请日：2004-11-23

申请人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

发明人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

IPC分类号： H01L21/8242

CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

公开(公告)号：US06849364B2

公开(公告)日：2005-02-01

申请号：US10226743

申请日：2002-08-23

申请人： Albrecht Kieslich ,  Hermann Sachse

发明人： Albrecht Kieslich ,  Hermann Sachse

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F1/36

摘要： A mask for fabricating semiconductor components contains first transparent regions and second transparent regions. The second regions are laid out such that they do not act on the regions of the photoresist directly beneath them in the exposure of the photoresist through the mask. The transparent regions define a size and a shape of structures to be formed.

摘要翻译： 用于制造半导体部件的掩模包含第一透明区域和第二透明区域。 第二区域布置成使得它们在通过掩模曝光光致抗蚀剂时不直接作用在其下的光刻胶的区域上。 透明区域限定要形成的结构的尺寸和形状。

公开(公告)号：US06750112B2

公开(公告)日：2004-06-15

申请号：US10178641

申请日：2002-06-24

申请人： Albrecht Kieslich

发明人： Albrecht Kieslich

IPC分类号： H01L2120

CPC分类号： H01L27/10885 ,  H01L27/10888

摘要： A method of forming a bitline and a bitline contact and a dynamic random access memory (DRAM) cell array includes the following steps. The bitline and the bitline contact are formed in a two-step process, in which, first, the bitline contact is formed in a first dielectric layer and, then, the bitline of a conductive material having a lower resistivity than the bitline contact material is defined in a second dielectric layer (5). According to a preferred embodiment, the second dielectric layer (5) is made of a low k dielectric. The retention anneal process, which is usually performed in the standard DRAM process, is preferably made before depositing the bitline material and, optionally, the low k dielectric. A dynamic random access memory cell array having at least one bitline and a bitline contact can be manufactured by this method.

摘要翻译： 形成位线和位线接触的方法以及动态随机存取存储器（DRAM）单元阵列包括以下步骤。 位线和位线接触以两步法形成，其中首先在第一电介质层中形成位线接触，然后，具有比位线接触材料低的电阻率的导电材料的位线是 限定在第二介电层（5）中。 根据优选实施例，第二电介质层（5）由低k电介质制成。 通常在标准DRAM工艺中进行的保留退火工艺优选在沉积位线材料和任选的低k电介质之前进行。 可以通过该方法制造具有至少一个位线和位线接触的动态随机存取存储单元阵列。