A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.