公开(公告)号：US06738880B2

公开(公告)日：2004-05-18

申请号：US09878896

申请日：2001-06-11

申请人： Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

发明人： Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

IPC分类号： G06F1300

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087

摘要： A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.

摘要翻译： 一种用于改变数据访问速度的缓冲区。 将缓冲器与诸如双倍数据速率同步动态随机存取存储器的存储器组合，可以提高存储器系统的数据传输速率。 缓冲器与控制芯片组和多个存储器模块耦合，以提供数据分析和组装的功能，以满足双向数据传输接口并获得更高的数据传输速率。 缓冲器还具有隔离两侧电气连接的功能。 来自存储器模块的单个信号接口可以由缓冲器转换成互补源同步信号，从而可以实现高速数据传输。 存储器系统可以应用若干这样的缓冲器以实现甚至更高的数据传输速度。

公开(公告)号：US06370053B2

公开(公告)日：2002-04-09

申请号：US09761880

申请日：2001-01-17

申请人： Nai-Shung Chang ,  Chia-Hsin Chen

发明人： Nai-Shung Chang ,  Chia-Hsin Chen

IPC分类号： G11C502

CPC分类号： H05K1/0246 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.

摘要翻译： 一个内存地址驱动电路，其内存模块插槽位于计算机主板上，可分为两组。 一组存储器模块插槽包括其控制芯片组的跟踪线小于2500密耳或最接近控制芯片组的插槽。 另一组内存模块插槽包括所有剩余的插槽。 控制芯片组包括两个存储器控制电路。 用于支持DDR DRAM的存储器控​​制电路连接到最靠近控制芯片组的存储器模块插槽的地址引线。 但是，没有端子电阻连接到内存模块插槽的任何地址引线。 因此，工程师可能只需要设计一组端子电阻。 此外，存储器控制电路使用一周期访问命令定时来提高系统性能。

公开(公告)号：US06446172B1

公开(公告)日：2002-09-03

申请号：US09335602

申请日：1999-06-18

申请人： Chia-Hsin Chen ,  Nai-Shung Chang

发明人： Chia-Hsin Chen ,  Nai-Shung Chang

IPC分类号： G06F1208

CPC分类号： G06F12/0859 ,  G06F13/161

摘要： A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method and system is characterized by, for each read request from the CPU, the prompt transfer of the corresponding internal read-request signal to the memory control unit, right after it is issued and without waiting until the CPU issues the L1 write-back signal of the current read request. If the current read request is a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back into the memory unit. This method and system can help reduce the period of waiting states by the CPU, thus increasing the overall memory access performance by the CPU and the overall system performance of the computer system.

摘要翻译： 提供存储器访问控制方法和系统，用于在计算机系统上以比现有技术更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。 这种存储器访问控制方法和系统的特征在于，对于来自CPU的每个读取请求，在相应的内部读取请求信号被发出之后立即将其传送到存储器控制单元，并且不等待直到CPU发出L1 当前读取请求的回写信号。 如果当前读取请求是对高速缓存存储器的命中，则立即发出读停止信号以停止对存储器单元的当前读取操作，然后执行高速缓存回写操作以将高速缓存数据写回到 存储单元 该方法和系统可以帮助减少CPU等待状态的时间，从而提高CPU的整体内存访问性能以及计算机系统的整体系统性能。

公开(公告)号：US07007175B2

公开(公告)日：2006-02-28

申请号：US10005627

申请日：2001-12-04

申请人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Chia-Hsin Chen

发明人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Chia-Hsin Chen

IPC分类号： G06F1/26

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  Y02D10/14 ,  Y02D50/20

摘要： A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

公开(公告)号：US06820219B1

公开(公告)日：2004-11-16

申请号：US09621750

申请日：2000-07-21

申请人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G06F1100

CPC分类号： G06F11/261 ,  G06F11/263

摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

摘要翻译： 提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。 在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。 这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。 在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。

公开(公告)号：US20050039083A1

公开(公告)日：2005-02-17

申请号：US10954509

申请日：2004-09-29

申请人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G06F7/58 ,  G06F11/00 ,  G06F11/26 ,  G06F11/263

CPC分类号： G06F11/261 ,  G06F11/263

摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

摘要翻译： 提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。 在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。 这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。 在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。

公开(公告)号：US06484281B1

公开(公告)日：2002-11-19

申请号：US09459763

申请日：1999-12-13

申请人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

摘要翻译： 提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试 模块，而不必使用两者。 该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为 包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。

公开(公告)号：US07723843B2

公开(公告)日：2010-05-25

申请号：US12354152

申请日：2009-01-15

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/34

CPC分类号： H01L23/367 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15321

摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

摘要翻译： 一种用于多封装模块的封装衬底。 封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。 凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。 还公开了一种具有封装基板的电子器件。

公开(公告)号：US07525182B2

公开(公告)日：2009-04-28

申请号：US11243121

申请日：2005-10-04

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/495

CPC分类号： H01L23/367 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15321

摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

摘要翻译： 一种用于多封装模块的封装衬底。 封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。 凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。 还公开了一种具有封装基板的电子器件。

公开(公告)号：US20070288782A1

公开(公告)日：2007-12-13

申请号：US11423722

申请日：2006-06-13

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/00

CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。