According to one embodiment, a RAM array includes at least one RAM cell comprising a first access transistor driven by a first word line. When the first access transistor is turned on, it couples the RAM cell to a first bit line. The first bit line is connected to a single-ended sense amplifier such as an inverter. Similarly, the RAM cell comprises second, third, and fourth access transistors driven by respectively second, third, and fourth word lines. When the respective access transistors are turned on, they couple the RAM cell to respectively second, third, and fourth bit lines. The bit lines are connected to respective single-ended sense amplifiers such as inverters. In one embodiment, each of the first, second, third, and fourth access transistors is an NFET. The first, second, third, and fourth bit lines are coupled to respectively first, second, third, and fourth precharge transistors.