发明授权
US06750123B2 Method of manufacturing CMOS device with implantation shielding layer
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制造具有植入屏蔽层的CMOS器件的方法
- 专利标题: Method of manufacturing CMOS device with implantation shielding layer
- 专利标题(中): 制造具有植入屏蔽层的CMOS器件的方法
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申请号: US09847288申请日: 2001-05-03
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公开(公告)号: US06750123B2公开(公告)日: 2004-06-15
- 发明人: Yasuaki Kawai
- 申请人: Yasuaki Kawai
- 优先权: JP2000-187143 20000622
- 主分类号: H01L21425
- IPC分类号: H01L21425
摘要:
A shielding layer 23 is selectively formed on a single crystal silicon layer, an active area 25 is formed in the single crystal silicon layer by using the shielding layer 23 as a mask and an impurity layer 26 is formed at the edges at the sides of the active area 25 by using the shielding layer 23 as a mask and implanting an impurity diagonally from above. As a result, since an impurity layer can be formed by implanting ions of the impurity at the edges at the sides of the active area even when the size of the active area is reduced to the absolute limit, the occurrence of the parasitic transistor phenomenon or the edge transistor phenomenon along the edges at the sides of the active area can be prevented.
公开/授权文献
- US20020001927A1 Semiconductor device manufacturing method 公开/授权日:2002-01-03