For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are connected to inputs of a clocked circuit to initiate data transfer and they apply a clock signal and a data signal, respectively. The variable delay is set within the range [tF−n&Dgr;t/2; tF+n&Dgr;t/2]. The fixed delay tF is at least n&Dgr;t/2. For calibration, the setting range of the variable delay and the fixed delay are each increased to the k-fold value and the variable delay is incremented in steps from n=0 until three phase changes are detected. The value of n at the first phase cycle completion corresponds to the variable delay for the set-up time and the value of n at the third phase cycle completion corresponds to the variable delay for the hold time.