DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write flag as count start point to start counting a predetermined number of clocks. The DRAM device uses a point at which the predetermined number of clocks have been counted as a taking-in start point of write data to take in the write data propagated through DQ bus. Transmission path of the write flag has topology equal to that of the transmission path of the write data. It can be considered that propagation delays in two transmission paths are equal. By the above defining of the taking-in start point, the DRAM device can appropriately take in the write data regardless of the propagation delay.