公开(公告)号：US06707743B2

公开(公告)日：2004-03-16

申请号：US10114282

申请日：2002-04-03

申请人： Wingyu Leung ,  Jae-Kwang Sim

发明人： Wingyu Leung ,  Jae-Kwang Sim

IPC分类号： G11C722

CPC分类号： G11C11/005 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40618

摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.

摘要翻译： 一种用于处理需要周期性刷新操作的DRAM阵列或其他存储器阵列的刷新的方法和装置，使得刷新不需要显式控制信号，也不需要在存储器阵列和外部存取客户端之间握手通信。 该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。 因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。 实现时钟分配方案，以允许在N个连续时钟周期内执行N个外部访问和一个刷新操作。

公开(公告)号：US06785189B2

公开(公告)日：2004-08-31

申请号：US10245437

申请日：2002-09-16

申请人： George M. Jacobs ,  James A. Duda

发明人： George M. Jacobs ,  James A. Duda

IPC分类号： G11C722

CPC分类号： G11C7/1066 ,  G06F13/4243

摘要： In a memory controller for use with a DDR SDRAM, an apparatus improves the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method adjusts the noise immunity provided by the apparatus. In particular DQS quality circuits frame the DQS signal for a predetermined portion of the READ operation.

摘要翻译： 在与DDR SDRAM一起使用的存储器控​​制器中，该装置提高了在读操作期间由DDR SDRAM提供的DQS信号上的噪声毛刺的控制器的抗扰度。 一种方法调节由该装置提供的噪声抗扰度。 特别地，DQS质量电路在DQ操作的预定部分上形成DQS信号。

公开(公告)号：US06768698B2

公开(公告)日：2004-07-27

申请号：US10255667

申请日：2002-09-27

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C722

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C2207/2227

摘要： A repeater receives an internal clock distributed from a DLL circuit irrespective of a data reading operation and outputs a DLL clock to a data output circuit and a data strobe signal output circuit in response to an internal signal only in the data reading operation. The data strobe signal output circuit receives the internal clock and the DLL clock, generates a data strobe signal in synchronization with the internal clock, and outputs the generated data strobe signal in synchronization with the DLL clock. As a result, a semiconductor memory device attains further reduction of power consumption during active-standby and a secure supply of the internal clock to a prescribed circuit.

摘要翻译： 中继器接收从DLL电路分配的内部时钟，与数据读取操作无关，并且仅在数据读取操作中响应于内部信号而将DLL时钟输出到数据输出电路和数据选通信号输出电路。 数据选通信号输出电路接收内部时钟和DLL时钟，与内部时钟同步产生数据选通信号，并与DLL时钟同步输出生成的数据选通信号。 结果，半导体存储器件在主动待机期间进一步降低功耗并且将内部时钟可靠地提供给规定的电路。

公开(公告)号：US06392957B1

公开(公告)日：2002-05-21

申请号：US09728377

申请日：2000-11-28

申请人： Alexander Shubat ,  Adam Kablanian ,  Jaroslav Raszka ,  Richard S. Roy

发明人： Alexander Shubat ,  Adam Kablanian ,  Jaroslav Raszka ,  Richard S. Roy

IPC分类号： G11C722

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C2207/104

摘要： A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the memory cycle time. The second reference cell may be any one of a conventional memory cell or write reference logic.

摘要翻译： 自定时的写入控制存储器件最小化阵列的单元的存储器周期时间。 自定时写控制存储器件优选地包括X解码器，字线驱动器，存储单元阵列，控制逻辑，预充电电路，读出放大器，参考解码器和参考字线驱动器。 存储器件优选地还包括第一参考单元，第二参考单元或逻辑，第一参考列，第二参考列和参考读出放大器。 第一参考单元优选地用于检测读周期完成，并且第二参考单元或逻辑用于检测写周期完成。 第一参考单元和第二参考单元的输出优选地耦合到唯一参考读出放大器的输入。 读出放大器包括专用电路，其使用第一参考单元或第二参考单元的输出来产生自定时钟，并且通过使存储器周期时间最小化。 第二参考单元可以是常规存储单元或写入参考逻辑中的任何一个。

公开(公告)号：US06762962B2

公开(公告)日：2004-07-13

申请号：US10357577

申请日：2003-02-04

申请人： Osamu Nagashima

发明人： Osamu Nagashima

IPC分类号： G11C722

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/229

摘要： DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write flag as count start point to start counting a predetermined number of clocks. The DRAM device uses a point at which the predetermined number of clocks have been counted as a taking-in start point of write data to take in the write data propagated through DQ bus. Transmission path of the write flag has topology equal to that of the transmission path of the write data. It can be considered that propagation delays in two transmission paths are equal. By the above defining of the taking-in start point, the DRAM device can appropriately take in the write data regardless of the propagation delay.

摘要翻译： 通过外部C / A总线，调节器和内部C / A总线从存储器控制器接收写入命令时，DRAM器件进入写入标志的等待状态。 在通过写入标志信号线从存储器控制器接收写入标志时，DRAM器件使用写入标志作为计数开始点开始计数预定数量的时钟。 DRAM装置使用预定数量的时钟被计数的点作为写入数据的接收开始点以获取通过DQ总线传播的写入数据。 写标志的传输路径具有与写数据的传输路径相同的拓扑。 可以认为两个传输路径中的传播延迟相等。 通过上述接收起始点的定义，DRAM器件可以适当地接收写入数据，而不管传播延迟如何。

公开(公告)号：US06754112B2

公开(公告)日：2004-06-22

申请号：US10074309

申请日：2002-02-11

申请人： Young-man Ahn ,  Jin-ho So ,  Byung-se So ,  Seung-jin Seo

发明人： Young-man Ahn ,  Jin-ho So ,  Byung-se So ,  Seung-jin Seo

IPC分类号： G11C722

CPC分类号： G11C7/1093 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

摘要翻译： 集成电路装置包括延迟电路，其被配置为延迟时钟信号，并且还被配置为响应于延迟的时钟信号和输入数据信号而产生输出数据信号。 多个设备被配置为响应于时钟信号分别接收输出数据信号。

公开(公告)号：US06731565B2

公开(公告)日：2004-05-04

申请号：US10064395

申请日：2002-07-10

申请人： Hsiang-I Huang

发明人： Hsiang-I Huang

IPC分类号： G11C722

CPC分类号： G06F13/1689

摘要： A programmable memory controller has a main memory device, a command decoder, a period setting device, a command-sequencing device and a command signal output device. When the programmable memory controller needs to access data inside a memory unit, the memory controller sends out a request signal. The command decoder receives the request signal and decodes the request signal to produce command signals. The period setting device receives a control signal and decodes the control signal to produce a period setting signal. The control signal controls the maintenance period of the command signals. The command-sequencing device receives the command signals and the period setting signals to sequence the command signals. The command signal output device receives the sequenced command signals and the period setting signal so that the sequenced command signal is sent to the memory unit during the maintenance period according to indications provided by the period setting signals.

摘要翻译： 可编程存储器控制器具有主存储器件，命令解码器，周期设置器件，命令排序器件和命令信号输出器件。 当可编程存储器控制器需要访问存储器单元内的数据时，存储器控制器发出请求信号。 命令解码器接收请求信号并解码请求信号以产生命令信号。 周期设定装置接收控制信号并解码该控制信号以产生周期设定信号。 控制信号控制命令信号的维护周期。 命令排序装置接收命令信号和周期设置信号以对命令信号进行排序。 命令信号输出装置接收顺序命令信号和周期设定信号，使得根据周期设定信号提供的指示，在维护期间将排序的命令信号发送到存储器单元。

公开(公告)号：US06370068B2

公开(公告)日：2002-04-09

申请号：US09755977

申请日：2001-01-05

申请人： Sang-Jae Rhee

发明人： Sang-Jae Rhee

IPC分类号： G11C722

CPC分类号： G11C7/1057 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051

摘要： Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

摘要翻译： 提供半导体器件及其数据采样方法，其中基于包含数据的存储单元阵列部分的相对位置从存储器单元阵列采样数据。 感测放大器响应于存储器单元阵列中的一个或多个单元的地址产生输出信号。 控制电路响应于存储器单元阵列中的一个或多个单元的地址的至少一部分（例如，地址的一个或多个高位）而产生采样控制信号。 然后，数据采样电路响应于采样控制信号对读出放大器的输出信号进行采样。 用于驱动控制电路的存储单元阵列地址的部分可逻辑地将存储单元阵列划分成两个或多个区段。 控制电路可以根据存储单元阵列部分与感测放大器的接近度来调整采样控制信号的定时。