发明授权
- 专利标题: Low power reduced voltage swing latch
- 专利标题(中): 低功耗降压摆动锁存器
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申请号: US10274191申请日: 2002-10-18
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公开(公告)号: US06768365B2公开(公告)日: 2004-07-27
- 发明人: Brian W. Curran , Edward T. Malley
- 申请人: Brian W. Curran , Edward T. Malley
- 主分类号: G06F104
- IPC分类号: G06F104
摘要:
An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.
公开/授权文献
- US20040075483A1 Low power reduced voltage swing latch 公开/授权日:2004-04-22
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