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    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY
    2.
    发明申请
    METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY 有权
    方法，计算机程序产品和用于消除或减少操作线交叉罚款的五金产品

    公开(公告)号：US20090240918A1

    公开(公告)日：2009-09-24

    申请号：US12051296

    申请日：2008-03-19

    申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3824

    摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

    摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

    Low power reduced voltage swing latch
    3.
    发明授权
    Low power reduced voltage swing latch 失效
    低功耗降压摆动锁存器

    公开(公告)号：US06768365B2

    公开(公告)日：2004-07-27

    申请号：US10274191

    申请日：2002-10-18

    申请人： Brian W. Curran ,  Edward T. Malley

    发明人： Brian W. Curran ,  Edward T. Malley

    IPC分类号： G06F104

    CPC分类号： G06F1/32 ,  G06F1/04

    摘要： An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.

    摘要翻译： 提供改进的时钟电路用于产生半摆时钟。 以前的电路操作需要额外的电源电压轨（Vdd / 2），但是优选实施例利用电荷共享来产生具有较少功率的半摆动时钟，而不需要额外的电源电压轨。 为了将时钟节点驱动到Vdd / 2，分路晶体管断开，完全充电的时钟节点与完全放电的时钟节点共享其电荷。 当电容正确匹配时，两个节点都将以Vdd / 2的速度进行定位。

    High performance, low power differential latch
    4.
    发明授权
    High performance, low power differential latch 失效
    高性能，低功耗差分锁存器

    公开(公告)号：US06657471B1

    公开(公告)日：2003-12-02

    申请号：US10290649

    申请日：2002-11-08

    申请人： Brian W. Curran ,  Edward T. Malley

    发明人： Brian W. Curran ,  Edward T. Malley

    IPC分类号： G11C706

    CPC分类号： H03K3/012 ,  H03K3/356139 ,  H03K3/356182

    摘要： An improved pull-down latch circuit is provided for better latch performance. Previous pull-down latch circuit performance is compromised during pull-up operation since weak PFETs are employed to pull up latch nodes. A pull up assist circuit is incorporated to assist weak PFET when latch node is being pulled up. The assist circuit is isolated from latch circuit when latch node is being pull down to guarantee that pull down circuit can overcome pull-up circuit (for correct latch operation).

    摘要翻译： 提供了一种改进的下拉锁存电路，用于更好的锁存性能。 在上拉操作期间，先前的下拉锁存电路性能受损，因为采用弱PFET来上拉锁存器节点。 当上拉闩锁节点时，引入一个上拉辅助电路来辅助弱PFET。 当锁存节点被拉下时，辅助电路与锁存电路隔离，以保证下拉电路可以克服上拉电路（用于正确的锁存器操作）。

    Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty
    5.
    发明授权
    Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty 有权
    方法，计算机程序产品和硬件产品，用于消除或减少操作线越界处罚

    公开(公告)号：US09201655B2

    公开(公告)日：2015-12-01

    申请号：US12051296

    申请日：2008-03-19

    申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/38

    CPC分类号： G06F9/3824

    摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

    摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

    Recycling long multi-operand instructions
    7.
    发明授权
    Recycling long multi-operand instructions 失效
    回收长操作数指令

    公开(公告)号：US07962726B2

    公开(公告)日：2011-06-14

    申请号：US12051215

    申请日：2008-03-19

    申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/30065 ,  G06F9/3832

    摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

    摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

    Low power overdriven pass gate latch
    8.
    发明授权
    Low power overdriven pass gate latch 失效
    低功耗过驱闸闸

    公开(公告)号：US06882205B2

    公开(公告)日：2005-04-19

    申请号：US10290636

    申请日：2002-11-08

    申请人： Brian W. Curran ,  Edward T. Malley

    发明人： Brian W. Curran ,  Edward T. Malley

    IPC分类号： G06F1/04 ,  G06F1/32

    CPC分类号： G06F1/32 ,  G06F1/04

    摘要： A clocking circuit decreases the load on the local clock signals to save power. The load is decreased by altering the structure of the latches. Typically, a passgate style latch is used where both an NFET and a PFET are used to control dataflow. Here, the PFET has been removed and the load is decreased. However, it is difficult to pass a logical 1 through an NFET and this increases both the rising slew and rising edge delay through the latch. The effect is mitigated, though, by overdriving the local clock block (LCB) local clocks to drive a local clock to the latches by passgates using only NFET transistors in the master latches and slave latches. Overdrivig the NFET gate allows the NFET to pass a full-level logical 1 signal.

    摘要翻译： 时钟电路减少本地时钟信号的负载，以节省功耗。 通过改变锁存器的结构来减小负载。 通常，使用通道式锁存器，其中NFET和PFET都用于控制数据流。 这里，PFET被去除并且负载减小。 然而，难以通过NFET传递逻辑1，并且通过锁存器增加上升的转换和上升沿延迟。 尽管如此，通过过驱动本地时钟块（LCB）本地时钟来驱动本地时钟到本地时钟，通过在主锁存器和从锁存器中仅使用NFET晶体管的通道来减轻效果。 过压NFET门允许NFET通过全电平逻辑1信号。

    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR
    9.
    发明申请
    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
    方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品

    公开(公告)号：US20090240922A1

    公开(公告)日：2009-09-24

    申请号：US12051792

    申请日：2008-03-19

    申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

    摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

    摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

    Operand and result forwarding between differently sized operands in a superscalar processor
    10.
    发明授权
    Operand and result forwarding between differently sized operands in a superscalar processor 失效
    操作数和结果在超标量处理器中的不同大小的操作数之间转发

    公开(公告)号：US07921279B2

    公开(公告)日：2011-04-05

    申请号：US12051792

    申请日：2008-03-19

    申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

    摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

    摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。