发明授权
US06771112B1 Semiconductor integrated circuit having pads with less input signal attenuation 有权
半导体集成电路具有输入信号衰减较小的焊盘

  • 专利标题: Semiconductor integrated circuit having pads with less input signal attenuation
  • 专利标题(中): 半导体集成电路具有输入信号衰减较小的焊盘
  • 申请号: US09552085
    申请日: 2000-02-24
  • 公开(公告)号: US06771112B1
    公开(公告)日: 2004-08-03
  • 发明人: Tsutomu IshikawaHiroshi Kojima
  • 申请人: Tsutomu IshikawaHiroshi Kojima
  • 优先权: JP11-050734 19990226; JP11-050735 19990226
  • 主分类号: H03K17687
  • IPC分类号: H03K17687
Semiconductor integrated circuit having pads with less input signal attenuation
摘要:
An integrated semiconductor device is provided that has pads with less input signal attenuation. When J-FET (2) is driven by an input signal, the current passing through it varies. The parasitic capacitance (4) is charged or discharged by the input/output signal of the buffer circuit (6) following the varying current. Thus, since the voltage across the parasitic capacitance (3) varies in phase and at the same level, the parasitic capacitance (3) can be ignored. This effect allows attenuation of an input signal due to the parasitic capacitance (3) to be prevented.
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