公开(公告)号：US06803680B2

公开(公告)日：2004-10-12

申请号：US10390957

申请日：2003-03-18

申请人： Christopher N. Brindle ,  Mark F. Kelcourse

发明人： Christopher N. Brindle ,  Mark F. Kelcourse

IPC分类号： H03K17687

CPC分类号： H03K17/102 ,  H01L27/0203 ,  H01L27/0629 ,  Y10T307/76

摘要： A sharp control voltage switch utilizing a plurality of field effect transistors (FETs) and a bypass resistance topology to sharpen the control voltage. Utilizing a total of six FETs allows the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

摘要翻译： 利用多个场效应晶体管（FET）和旁路电阻拓扑来锐化控制电压的尖锐的控制电压开关。 使用总共六个FET可以使开关在低控制电压下工作，而不需要增加器件周边或管芯尺寸。 连接在最上面的FET的栅极和源极之间的前馈电容器和最下面的FET的栅极和漏极被用于减少信号失真并提高开关内的FET的线性度和谐波抑制特性，从而降低谐波 开关。

公开(公告)号：US06696881B1

公开(公告)日：2004-02-24

申请号：US10358500

申请日：2003-02-04

申请人： Kenneth Ho

发明人： Kenneth Ho

IPC分类号： H03K17687

CPC分类号： G05F3/262

摘要： A method and apparatus for compensating for gate current through a first capacitor includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The biasing circuit ensures the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. In addition, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”. As a result, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through second compensation transistor.

摘要翻译： 用于补偿通过第一电容器的栅极电流的方法和装置包括：偏置电路; 第一补偿晶体管; 第二补偿晶体管; 和补偿电容器。 偏置电路确保补偿电容器两端的偏置电压等于第一电容器两端的偏置电压。 此外，选择第二补偿晶体管的尺寸，使得如果补偿电容器的面积除以第一电容器的面积的比率是面积比“AR”，则第一补偿器的尺寸的比率 晶体管除以第二补偿晶体管的大小也是面积比“AR”。 结果，根据本发明的方法和装置，通过第一电容器的栅极电流Ig等于通过第二补偿晶体管排出的电流。

公开(公告)号：US06605978B1

公开(公告)日：2003-08-12

申请号：US10254274

申请日：2002-09-25

申请人： Josef Halamik ,  Frantisek Sukup

发明人： Josef Halamik ,  Frantisek Sukup

IPC分类号： H03K17687

CPC分类号： G01R19/0084

摘要： A voltage detection device (10, 30) utilizes grounded gate J-FET transistors (16,17,18) to detect desired input voltage values. The grounded gate J-FET transistors (16,17,18) function in different modes as the input voltage varies to facilitate detecting the desired input voltage values.

摘要翻译： 电压检测装置（10,30）利用接地栅极J-FET晶体管（16,17,18）来检测期望的输入电压值。 当输入电压变化时，接地栅极J-FET晶体管（16,17,18）以不同的模式工作，以便于检测所需的输入电压值。

公开(公告)号：US06529056B1

公开(公告)日：2003-03-04

申请号：US10172484

申请日：2002-06-13

申请人： Budong You ,  Marco A. Zuniga

发明人： Budong You ,  Marco A. Zuniga

IPC分类号： H03K17687

CPC分类号： H03K17/167 ,  H03K5/08 ,  H03K5/15 ,  H03K17/302

摘要： A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.

摘要翻译： 一种与具有场效应晶体管（FET）的开关一起使用的电路和方法和计算机程序产品。 该方法和计算机程序产品包括将FET的漏极 - 源极电压限制在预定范围内; 然后切换FET。 通常，一方面，本发明的特征在于具有源极，漏极和栅极端子的电路。 电路包括具有耦合到漏极端子的第一漏极和耦合到源极端子的第一源极的第一FET; 第二FET，具有耦合到所述漏极端子的第二漏极和耦合到所述源极端子的第二源极; 以及耦合到所述栅极端子，所述第一栅极和所述第二栅极的控制电路。

公开(公告)号：US06486715B2

公开(公告)日：2002-11-26

申请号：US09825615

申请日：2001-04-02

申请人： Geoffrey S. Gongwer ,  Shahzad Khalid

发明人： Geoffrey S. Gongwer ,  Shahzad Khalid

IPC分类号： H03K17687

CPC分类号： G11C5/145 ,  G11C8/08

摘要： Driver (100) and method are provided for driving capacitive load (120) that achieve an improved response time without increasing power consumption of the driver. Driver (100) has load buffer (105) with an input (110) for receiving an input voltage (VIN), and an output 115 for coupling an output voltage (VOUT) to load 120. VOUT is driven between a first voltage level (V1) and a second voltage level (V2) in response to changes in VIN. Driver (100) also has reserve circuit (125) with capacitor (130), reserve buffer (135), switch (140) for coupling the capacitor to capacitive load (120) and controller (145) for operating the switch. Reserve buffer (135) has an input (150) for receiving an input voltage (VRES—IN), and an output (155) for coupling an output voltage (VRES—OUT) to capacitor (130) to charge the capacitor. Controller (145) is configured to operate switch (140) to couple capacitor (130) to capacitive load (120) when VOUT is being driven between V1 and V2.

摘要翻译： 驱动器（100）和方法被提供用于驱动电容性负载（120），其实现改善的响应时间，而不增加驱动器的功率消耗。 驱动器（100）具有负载缓冲器（105），其具有用于接收输入电压（VIN）的输入端（110）和用于将输出电压（VOUT）耦合到负载120的输出端115.VOUT在第一电压电平 V1）和响应于VIN变化的第二电压电平（V2）。 驱动器（100）还具有用于将电容器耦合到电容性负载（120）的开关（140）和用于操作开关的控制器（145）的具有电容器（130），保留缓冲器（135）的开关（140）。 保留缓冲器（135）具有用于接收输入电压（VRES-IN）的输入端（150）和用于将输出电压（VRES-OUT）耦合到电容器（130）以对电容器充电的输出端（155）。 当VOUT在V1和V2之间被驱动时，控制器（145）被配置为操作开关（140）以将电容器（130）耦合到电容性负载（120）。

公开(公告)号：US06483369B1

公开(公告)日：2002-11-19

申请号：US09970365

申请日：2001-10-02

申请人： Ernest H. Wittenbreder, Jr.

发明人： Ernest H. Wittenbreder, Jr.

IPC分类号： H03K17687

CPC分类号： H03K17/102 ,  H03K17/04163 ,  H03K17/08142 ,  H03K17/687 ,  H03K17/6877

摘要： Composite switches comprising multiple mosfets arranged in cascode which achieve higher efficiency and faster switching are revealed. The gate of a lower mosfet, a low voltage small die size mosfet, is driven with a conventional control circuit for modulation of the composite switch. The upper mosfet, a large die size high voltage mosfet, is controlled at its source terminal by the smaller mosfet while the gate of the upper mosfet is connected to a capacitor whose voltage remains fixed such that no net drive power is required by the gate circuit to drive the upper mosfet. The composite switch simultaneously achieves the low conduction losses of a large die device with the gate drive losses and fast switching of a small die device.

摘要翻译： 显示了包括以共源共栅布置的多个mosfet的复合开关，其实现更高的效率和更快的切换。 低级mosfet的栅极，低压小型芯片尺寸的mosfet，由传统的控制电路驱动，用于复合开关的调制。 上部mosfet是一个大型芯片尺寸的高压MOSFET，它的源极端子由较小的mosfet控制，而上部mosfet的栅极连接到电压保持固定的电容器，使栅极电路不需要净功率 驱动上面的mosfet。 复合开关同时通过栅极驱动损耗和小型器件的快速切换实现了大型器件的低导通损耗。

公开(公告)号：US06348831B1

公开(公告)日：2002-02-19

申请号：US09465774

申请日：1999-12-17

申请人： Fujio Baba

发明人： Fujio Baba

IPC分类号： H03K17687

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/162 ,  H03K17/6872 ,  H03K2217/0018 ,  H03K2217/0036

摘要： A semiconductor device comprises an analog switch and digital circuitry, both of which are formed on a single integrated circuit chip and share a node coupled to external circuitry. A first power source, provided in the device, is coupled to an input terminal of the analog switch whose output is operatively coupled to the node, and a second power source is also provided so as to supply electric power to the digital circuitry whose input or output is operatively coupled to the node. A back gate voltage controller, coupled to a back gate of the analog switch, is provided in order to control a voltage applied to the back gate in response to an operation mode control signal for determining whether the analog switch or the digital circuitry is to be enabled.

摘要翻译： 半导体器件包括模拟开关和数字电路，它们都形成在单个集成电路芯片上并且共享耦合到外部电路的节点。 设置在设备中的第一电源耦合到模拟开关的输入端，该输出端的输出可操作地耦合到该节点，并且还提供第二电源，以向其数字电路提供电力，该数字电路的输入或 输出可操作地耦合到节点。 提供耦合到模拟开关的背栅的背栅电压控制器，以响应于用于确定模拟开关或数字电路是否将被操作的操作模式控制信号来控制施加到背栅的电压 启用

公开(公告)号：US06320449B1

公开(公告)日：2001-11-20

申请号：US09692133

申请日：2000-10-19

申请人： Salvatore Vincenzo Capici ,  Filippo Marino

发明人： Salvatore Vincenzo Capici ,  Filippo Marino

IPC分类号： H03K17687

CPC分类号： H03K17/687 ,  H03K17/04123

摘要： The invention relates to a driver circuit for P-channel MOS switches including a power transistor having a control terminal and first and second conduction terminals, a controlled current generator connected to the control terminal for turning on the power transistor, a control circuit for controlling the turning on of the current generator, and a protection circuit coupled to the control terminal. The driver circuit may also include a second current generator connected to the control terminal of the power transistor which is in turn driven by the control circuit to control the transistor turn-off. Advantageously, the control circuit may also receive a control signal from the protection circuit at the end of the latter's action.

摘要翻译： 本发明涉及一种用于P沟道MOS开关的驱动电路，包括具有控制端和第一和第二导通端的功率晶体管，连接到用于接通功率晶体管的控制端的受控电流发生器，控制电路 接通电流发生器，以及保护电路，耦合到控制端。 驱动器电路还可以包括连接到功率晶体管的控制端子的第二电流发生器，该第二电流发生器又由控制电路驱动以控制晶体管截止。 有利地，控制电路还可以在后者的动作结束时从保护电路接收控制信号。

公开(公告)号：US06313690B1

公开(公告)日：2001-11-06

申请号：US09502008

申请日：2000-02-11

申请人： Shunzou Ohshima

发明人： Shunzou Ohshima

IPC分类号： H03K17687

CPC分类号： H03K17/0822 ,  H03K2017/0806

摘要： First main electrodes of second and third semiconductor elements are connected to the first main electrode of the first semiconductor element, control electrodes of the second and third semiconductor elements are connected to the control electrode of the first semiconductor element, a second main electrode of the second semiconductor element is connected to a first resistor, and a second main electrode of the third semiconductor element is connected to a second resistor. Second main-electrode voltages of the first and second semiconductor elements are compared with each other by a first comparator, a control voltage is supplied a control voltage to the control electrodes of the first and second semiconductor elements according to an output of the first comparator by control means. Second main-electrode voltages of the first and third semiconductor elements are compared with each other by a second comparator. The transistor widths of the second and third semiconductor elements are each smaller than the transistor width of the first semiconductor element. The first semiconductor element is connected to power supply elements in parallel with one another between a power source and a load, and a weak current is detected when the load and power supply elements are OFF. There is no shunt resistor when detecting an overcurrent or a weak current. Accordingly, a heat loss is minimized and detective sensitivity is improved.

摘要翻译： 第二和第三半导体元件的第一主电极连接到第一半导体元件的第一主电极，第二和第三半导体元件的控制电极连接到第一半导体元件的控制电极，第二主电极连接到第二半导体元件的第二主电极 半导体元件连接到第一电阻器，并且第三半导体元件的第二主电极连接到第二电阻器。 通过第一比较器将第一和第二半导体元件的第二主电极电压彼此进行比较，根据第一比较器的输出，向第一和第二半导体元件的控制电极提供控制电压控制电压 控制手段。 通过第二比较器将第一和第三半导体元件的第二主电极电压彼此进行比较。 第二和第三半导体元件的晶体管宽度均小于第一半导体元件的晶体管宽度。 第一半导体元件在电源和负载之间彼此并联连接到电源元件，并且当负载和电源元件关闭时检测到弱电流。 检测到过电流或弱电流时，没有分流电阻。 因此，热损失最小化，提高了检测灵敏度。

公开(公告)号：US06275093B1

公开(公告)日：2001-08-14

申请号：US09030871

申请日：1998-02-25

申请人： Sampat Singh Shekhawat ,  Jon Gladish ,  Anup Bhalla

发明人： Sampat Singh Shekhawat ,  Jon Gladish ,  Anup Bhalla

IPC分类号： H03K17687

CPC分类号： H03K17/0828

摘要： An IGBT gate driver circuit includes means for detecting when the collector-to-emitter voltage (Vce) of a turned-on IGBT, intended to be operated in the saturation region, increases above a preset level, indicative of a fault condition, such as a short circuit. In response to such an increase in the Vce of a turned on IGBT, the IGBT is turned-off in two steps. First, the turn-on gate drive is decreased to a level that is still above the threshold (turn-on) voltage of the IGBT in order to decrease the current flowing through the IGBT and hence, the peak power dissipation. This decrease in the current through the IGBT and the peak power dissipation increases the length of time the IGBT can withstand a fault condition such as a short circuit. Then, after decreasing the gate drive to the IGBT, the gate drive is gradually decreased until the IGBT is completely turned off.

摘要翻译： IGBT栅极驱动器电路包括用于检测旨在在饱和区域中操作的导通IGBT的集电极 - 发射极电压（Vce）何时增加到指示故障状态的预设电平以上的装置，例如 短路。 响应于导通IGBT的Vce的这种增加，IGBT分两个阶段关断。 首先，导通栅极驱动被降低到仍然高于IGBT的阈值（导通）电压的电平，以便减小流过IGBT的电流，并因此降低峰值功耗。 通过IGBT的电流的降低和峰值功率耗散增加了IGBT能够经受诸如短路的故障状态的时间长度。 然后，在将栅极驱动减少到IGBT之后，栅极驱动逐渐减小，直到IGBT完全关断。