Invention Grant
- Patent Title: Semiconductor integrated circuit device having multilevel interconnection
- Patent Title (中): 具有多层互连的半导体集成电路器件
-
Application No.: US10717556Application Date: 2003-11-21
-
Publication No.: US06774024B2Publication Date: 2004-08-10
- Inventor: Koji Miyamoto , Kenji Yoshida , Hisashi Kaneko
- Applicant: Koji Miyamoto , Kenji Yoshida , Hisashi Kaneko
- Priority: JP2002-212908 20020722
- Main IPC: H01L2972
- IPC: H01L2972

Abstract:
One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
Public/Granted literature
- US20040104482A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING MULTILEVEL INTERCONNECTION Public/Granted day:2004-06-03
Information query