发明授权
US06774731B2 Method and circuit for minimizing glitches in phase-locked loops
有权
用于最大限度地减少锁相环路中的毛刺的方法和电路
- 专利标题: Method and circuit for minimizing glitches in phase-locked loops
- 专利标题(中): 用于最大限度地减少锁相环路中的毛刺的方法和电路
-
申请号: US10244113申请日: 2002-09-13
-
公开(公告)号: US06774731B2公开(公告)日: 2004-08-10
- 发明人: Antonio Magazzu , Benedetto Marco Marletta , Giuseppe Gramegna , Alessandro D'Aquila
- 申请人: Antonio Magazzu , Benedetto Marco Marletta , Giuseppe Gramegna , Alessandro D'Aquila
- 优先权: EP99830234 19990421
- 主分类号: H03L706
- IPC分类号: H03L706
摘要:
A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.
公开/授权文献
信息查询