- 专利标题: Multilayer electrode for a ferroelectric capacitor
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申请号: US09930960申请日: 2001-08-17
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公开(公告)号: US06777739B2公开(公告)日: 2004-08-17
- 发明人: Vishnu K. Agarwal , Garo J. Derderian , F. Daniel Gealy
- 申请人: Vishnu K. Agarwal , Garo J. Derderian , F. Daniel Gealy
- 主分类号: H01L31119
- IPC分类号: H01L31119
摘要:
A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.
公开/授权文献
- US20010052609A1 Multilayer electrode for a ferroelectric capacitor 公开/授权日:2001-12-20
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