A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write clock. The FIFO includes a read counter responsive to the internal clock to identify a current read address in the FIFO. At a given cycle of the internal clock, the word stored at the current read address of the FIFO may be registered within the registers of the programmable semiconductor device.