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    FIFO memory architecture
    1.
    发明授权
    FIFO memory architecture 有权
    FIFO存储器架构

    公开(公告)号：US06777979B1

    公开(公告)日：2004-08-17

    申请号：US10334642

    申请日：2002-12-31

    申请人： Jinghui Zhu ,  Jin Ni ,  Ju Shen ,  Tong-Sheng Wang

    发明人： Jinghui Zhu ,  Jin Ni ,  Ju Shen ,  Tong-Sheng Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17744

    摘要： A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write clock. The FIFO includes a read counter responsive to the internal clock to identify a current read address in the FIFO. At a given cycle of the internal clock, the word stored at the current read address of the FIFO may be registered within the registers of the programmable semiconductor device.

    摘要翻译： FIFO与可编程半导体器件的寄存器协调，其中寄存器根据内部时钟计时，并且根据写时钟将字写入FIFO。 FIFO包括响应于内部时钟的读取计数器，以识别FIFO中的当前读取地址。 在内部时钟的给定周期，存储在FIFO的当前读取地址处的字可以被注册在可编程半导体器件的寄存器内。

    SERDES with programmable I/O architecture
    2.
    发明授权
    SERDES with programmable I/O architecture 有权
    SERDES具有可编程I / O架构

    公开(公告)号：US07208975B1

    公开(公告)日：2007-04-24

    申请号：US11040772

    申请日：2005-01-20

    申请人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

    发明人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

    摘要翻译： 在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。 布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路 具有确定性的路由延迟。 在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

    SERDES with programmable I/O architecture
    3.
    发明授权
    SERDES with programmable I/O architecture 有权
    SERDES具有可编程I / O架构

    公开(公告)号：US07327160B1

    公开(公告)日：2008-02-05

    申请号：US11676196

    申请日：2007-02-16

    申请人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

    发明人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.

    摘要翻译： 在本发明的一个实施例中，可编程集成电路包括多个SERDES电路; 多个输入/输出（I / O）电路; 以及可配置为通过具有确定性路由延迟的路由路径提供一个或多个以下连接的路由结构：将SERDES电路耦合到另一个SERDES电路; 将SERDES电路耦合到I / O电路; 将I / O电路耦合到SERDES电路; 并将I / O电路耦合到另一个I / O电路。

    Programmable logic device with enhanced logic block architecture
    4.
    发明授权
    Programmable logic device with enhanced logic block architecture 有权
    具有增强逻辑块架构的可编程逻辑器件

    公开(公告)号：US07573291B1

    公开(公告)日：2009-08-11

    申请号：US11934711

    申请日：2007-11-02

    申请人： Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

    发明人： Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728

    摘要： A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

    摘要翻译： 可编程逻辑器件内的可编程逻辑块包括至少两个互连的片，每个互连片包括至少两个互连的查找表。 每个互连的查找表适于从路由结构接收输入信号并提供LUT输出信号。 至少一个切片包括适于注册查找表的LUT输出信号的寄存器，并且至少另一个切片包括比查找表少的这样的寄存器。

    Register data retention systems and methods during reprogramming of programmable logic devices
    5.
    发明授权
    Register data retention systems and methods during reprogramming of programmable logic devices 有权
    在可编程逻辑器件重新编程期间注册数据保留系统和方法

    公开(公告)号：US07535253B1

    公开(公告)日：2009-05-19

    申请号：US11941006

    申请日：2007-11-15

    申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

    发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17772 ,  H03K19/1776

    摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.

    摘要翻译： 根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。 例如，根据实施例，一种方法包括在可编程逻辑和可编程逻辑器件的寄存器之间编程路由资源，以在重新编程之前提供用于数据的数据路径; 在重新编程之前，通过数据路径将数据从可编程逻辑转移到寄存器，以便在重新编程期间将数据存储在可编程逻辑器件内; 重新编程可编程逻辑器件，其中重新编程在可编程逻辑器件和可编程逻辑器件的寄存器之间提供重新编程的数据通路; 并且在可编程逻辑器件的重新编程已经完成之后，通过可编程逻辑器件从寄存器传送数据以供可编程逻辑使用。

    Array of configurable logic blocks including cascadable lookup tables
    7.
    发明授权
    Array of configurable logic blocks including cascadable lookup tables 失效
    可配置逻辑块的数组，包括级联查找表

    公开(公告)号：US5586044A

    公开(公告)日：1996-12-17

    申请号：US461196

    申请日：1995-06-05

    申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

    发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

    IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

    摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's that share a same plurality of input signals where the output of one of the LUT's is connectable by direct connect means to an input of a further pair of LUT's.

    摘要翻译： 可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。 每个CLB包括由比特存储区域定义的多个功能查找表（LUT）和响应于用于选择存储的比特的输入信号的选择装置。 该设计包括共享相同多个输入信号的第一和第二LUT，其中一个LUT的输出可以通过直接连接装置连接到另一对LUT的输入。

    Programmable gate array device having cascaded means for function definition
    8.
    发明授权
    Programmable gate array device having cascaded means for function definition 失效
    具有用于功能定义的级联装置的可编程门阵列器件

    公开(公告)号：US5422823A

    公开(公告)日：1995-06-06

    申请号：US271872

    申请日：1994-07-07

    申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

    发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

    IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

    摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

    摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

    Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device
    9.
    发明授权
    Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device 失效
    可编程逻辑器件提供产品术语共享和转向可编程逻辑器件的输出

    公开(公告)号：US5130574A

    公开(公告)日：1992-07-14

    申请号：US696461

    申请日：1991-05-06

    申请人： Ju Shen ,  Albert L. Chan ,  Kapil Shankar ,  Cyrus Tsui

    发明人： Ju Shen ,  Albert L. Chan ,  Kapil Shankar ,  Cyrus Tsui

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708

    摘要： A programmable logic device is disclosed which includes a programmable AND array, a plurality of logic circuits connected to groups of product term outputs from the AND array for performing a logical OR operation of the product term inputs and the programmable logic device includes programmable OR circuitry for selectively connecting one or more of the ORed groups of product terms to one or more outputs of the programmable logic device. The programmable OR circuit permits product term steering and sharing.

    摘要翻译： 公开了一种可编程逻辑器件，其包括可编程AND阵列，多个逻辑电路连接到来自AND阵列的产品项输出组，用于执行产品项输入的逻辑或运算，并且可编程逻辑器件包括可编程OR电路 选择性地将一个或多个OR组的产品术语连接到可编程逻辑器件的一个或多个输出。 可编程OR电路允许产品术语转向和共享。

    Register data retention systems and methods during reprogramming of programmable logic devices
    10.
    发明授权
    Register data retention systems and methods during reprogramming of programmable logic devices 有权
    在可编程逻辑器件重新编程期间注册数据保留系统和方法

    公开(公告)号：US07876125B1

    公开(公告)日：2011-01-25

    申请号：US12464822

    申请日：2009-05-12

    申请人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

    发明人： Howard Tang ,  Roger Spinti ,  San-Ta Kow ,  Ju Shen

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17772 ,  H03K19/1776

    摘要： Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.

    摘要翻译： 根据本发明的一个或多个实施例，系统和方法为可编程逻辑器件提供寄存器数据保留技术。 例如，在一个实施例中，可编程逻辑器件包括适于在可编程逻辑器件的操作期间生成用户数据的多个逻辑块; 多个寄存器，适于在可编程逻辑器件的重新编程操作期间存储用户数据; 以及适于在逻辑块和寄存器之间提供编程数据路径的可配置路由资源。