An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.