Invention Grant
US06787439B2 Method using planarizing gate material to improve gate critical dimension in semiconductor devices
有权
使用平面化栅极材料来改善半导体器件中的栅极临界尺寸的方法
- Patent Title: Method using planarizing gate material to improve gate critical dimension in semiconductor devices
- Patent Title (中): 使用平面化栅极材料来改善半导体器件中的栅极临界尺寸的方法
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Application No.: US10290276Application Date: 2002-11-08
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Publication No.: US06787439B2Publication Date: 2004-09-07
- Inventor: Shibly S. Ahmed , Cyrus E. Tabery , Haihong Wang , Bin Yu
- Applicant: Shibly S. Ahmed , Cyrus E. Tabery , Haihong Wang , Bin Yu
- Main IPC: H01L213205
- IPC: H01L213205

Abstract:
A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.
Public/Granted literature
- US20040092062A1 Planarizing gate material to improve gate critical dimension in semiconductor devices Public/Granted day:2004-05-13
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