Invention Grant
- Patent Title: Self-aligned vias in an integrated circuit structure
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Application No.: US10212419Application Date: 2002-08-05
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Publication No.: US06787875B2Publication Date: 2004-09-07
- Inventor: Kenneth D. Brennan , Paul M. Gillespie
- Applicant: Kenneth D. Brennan , Paul M. Gillespie
- Main IPC: H01L2972
- IPC: H01L2972

Abstract:
A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.
Public/Granted literature
- US20040021196A1 Self-aligned vias in an integrated circuit structure Public/Granted day:2004-02-05
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