发明授权
- 专利标题: Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
- 专利标题(中): 在集成电路生产中电镀高纯度铜导体结构的方法
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申请号: US09831763申请日: 2001-05-11
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公开(公告)号: US06793795B1公开(公告)日: 2004-09-21
- 发明人: Heinrich Meyer , Andreas Thies
- 申请人: Heinrich Meyer , Andreas Thies
- 优先权: DE19903178 19990121; DE19915146 19990326
- 主分类号: C25D2118
- IPC分类号: C25D2118
摘要:
A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer. The electrolytic metal deposition method is accomplished by bringing the semiconductor substrates into contact with a copper deposition bath containing at least one copper ion source, at least one additive compound for controlling the physico-mechanical properties of the copper layers, and Fe(II) and/or Fe(III) compounds, and applying an electric voltage between the semiconductor substrates and dimensionally stable counter-electrodes.
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