Invention Grant
- Patent Title: Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
- Patent Title (中): 堆叠电容器及其形成方法以及使用其的半导体器件以及使用其的电路板
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Application No.: US10085116Application Date: 2002-03-01
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Publication No.: US06794729B2Publication Date: 2004-09-21
- Inventor: Toru Mori , Takao Yamakazi , Koichiro Nakase
- Applicant: Toru Mori , Takao Yamakazi , Koichiro Nakase
- Priority: JP2001-056950 20010301
- Main IPC: H01L27108
- IPC: H01L27108
Abstract:
A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.
Public/Granted literature
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