公开(公告)号：US07981532B2

公开(公告)日：2011-07-19

申请号：US12088389

申请日：2006-09-28

Applicant: Toru Mori ,  Yoshimi Kubo ,  Akira Okamoto ,  Yasuyuki Nakamura

Inventor： Toru Mori ,  Yoshimi Kubo ,  Akira Okamoto ,  Yasuyuki Nakamura

IPC: C01F17/00 ,  B32B9/00

CPC classification number: C09K5/08 ,  C01G45/1264 ,  C01P2002/34 ,  C03C17/23 ,  C03C17/3417 ,  C03C17/3435 ,  C03C2217/23

Abstract: In an Mn-containing perovskite oxide which is a conventional phase-change substance (A1−xBx)MnO3, when the mixing amount x is increased, the transition temperature (Tc) is shifted to higher temperature side, but the slope of a change in the emittance become gentle and Δε (ε at higher temperature−ε at lower temperature) also become small. In the present invention, the compositional formula of the phase-change substance is the Mn-containing perovskite oxide represented by (A1−xBx)Mn1+yO3 with 0

Abstract translation: 在常规相变物质（A1-xBx）MnO3的含Mn钙钛矿氧化物中，当混合量x增加时，转变温度（Tc）转变到较高温度侧，但是斜率 放射性变得温和，并且 （在较高温度下，在较低温度下）也变小。 在本发明中，相变物质的组成式是由（A1-xBx）Mn1 + yO3表示的含有Mn的钙钛矿氧化物，其中Mn比由化学计量组成变化，从而使转变 温度（Tc）升高到更高的温度，其发射特性与具有从化学计量组成不变的组成的相变物质相当。

公开(公告)号：US20110165770A1

公开(公告)日：2011-07-07

申请号：US13064204

申请日：2011-03-10

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L21/28

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Abstract translation: 非易失性存储器件包括形成在半导体衬底上以存储预定信息的存储单元区域和形成在半导体衬底上的外围电路区域。 存储单元区域包括栅电极; 和电荷存储层，所述电荷存储层形成为具有延伸到所述栅电极的底端的两侧的边缘的凹口或楔形。 外围电路区域中不包含电荷存储层。

公开(公告)号：US07923765B2

公开(公告)日：2011-04-12

申请号：US12314956

申请日：2008-12-19

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L29/788 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

公开(公告)号：US20090159960A1

公开(公告)日：2009-06-25

申请号：US12314956

申请日：2008-12-19

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Abstract translation: 非易失性存储器件包括形成在半导体衬底上以存储预定信息的存储单元区域和形成在半导体衬底上的外围电路区域。 存储单元区域包括栅电极; 和电荷存储层，所述电荷存储层形成为具有延伸到所述栅电极的底端的两侧的边缘的凹口或楔形。 外围电路区域中不包含电荷存储层。

公开(公告)号：US07323537B2

公开(公告)日：2008-01-29

申请号：US11291975

申请日：2005-12-02

Applicant: Hitoshi Nimura ,  Motohiro Munakata ,  Toru Mori ,  Toshio Akai

Inventor： Hitoshi Nimura ,  Motohiro Munakata ,  Toru Mori ,  Toshio Akai

IPC: C08G63/02

CPC classification number: C08G63/85 ,  C08G63/183 ,  C08G63/83

Abstract: To provide a catalyst for production of a polyester, a process for producing a polyester using the catalyst and a titanium-containing polyethylene terephthalate having excellent characteristics.A catalyst for production of a polyester, characterized by comprising at least (1) a Group 4A compound (hereinafter referred to as compound (1)), (2) a compound of at least one element selected from the group consisting of magnesium, calcium and zinc (hereinafter referred to as compound (2)) and an oxygen-containing organic solvent. A process for producing a polyester using this catalyst. A titanium-containing polyethylene terephthalate, having characteristics represented by the following (A), (B) and (C): (A) titanium K absorption edge: the peak intensity ratio R defined by R=A/B exceeds 0.2, where A is the intensity of a peak having the maximum intensity among K absorption pre-edge peaks, and B is the maximum peak intensity of K absorption post-edge peaks in a XANES spectrum obtained by normalizing a XAFS spectrum; (B) the amount of carboxyl end groups is less than 35 eq/ton; and (C) the intrinsic viscosity is at least 0.5 dl/g.

Abstract translation: 提供生产聚酯的催化剂，使用该催化剂生产聚酯的方法和具有优异特性的含钛聚对苯二甲酸乙二醇酯。 一种生产聚酯的催化剂，其特征在于至少包含（1）4A族化合物（以下称为化合物（1）），（2）至少一种选自镁，钙 和锌（以下称为化合物（2））和含氧有机溶剂。 使用该催化剂制造聚酯的方法。 具有以下（A），（B）和（C）表示的特征的含钛聚对苯二甲酸乙二醇酯：（A）钛K吸收边：由R = A / B定义的峰强度比R超过0.2，其中A 是K吸收前缘峰中具有最大强度的峰的强度，B是通过归一化XAFS光谱获得的XANES光谱中的K吸收后边缘峰的最大峰强度; （B）羧基端基的量小于35当量/吨; 和（C）特性粘度为至少0.5dl / g。

公开(公告)号：US07087967B2

公开(公告)日：2006-08-08

申请号：US10648784

申请日：2003-08-27

Applicant: Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

Inventor： Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract translation: LSI器件包括施加第一驱动电压的芯区域和施加高于上述第一驱动电压的第二驱动电压的接口区域。 LSI器件包括SOI衬底和用于将SOI衬底的SOI层分离成芯区域和界面区域的器件分离区域。 芯区域的SOI层的厚度比界面区域的SOI层的厚度薄。 LSI器件还包括形成在芯区域中的第一MOSFET，其中芯区的SOI层是完全耗尽的Si沟道，并且在界面区域中形成第二MOSFET，并且其中界面区域的SOI层是完全耗尽的 Si通道。

公开(公告)号：US06924183B2

公开(公告)日：2005-08-02

申请号：US10748259

申请日：2003-12-31

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section which penetrates the first insulation film, element isolation region and a buried oxide film to expose the support substrate. The method also includes creating a first source interconnect, first drain interconnect and first gate interconnect which are electrically connected to the transistors, on the second insulation film. The method also includes forming dummy interconnects which are connected with these interconnects, and are electrically connected with the support substrate via the first opening section, on the second insulation film. The method also includes disconnecting the dummy interconnects to electrically insulate the first source interconnect, first drain interconnect and first gate interconnect from the support substrate.

公开(公告)号：US06515324B2

公开(公告)日：2003-02-04

申请号：US09942817

申请日：2001-08-30

Applicant: Akinobu Shibuya ,  Shintaro Yamamichi ,  Toru Mori ,  Takao Yamazaki ,  Yuzo Shimada

Inventor： Akinobu Shibuya ,  Shintaro Yamamichi ,  Toru Mori ,  Takao Yamazaki ,  Yuzo Shimada

IPC: H01L27178

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A capacitor has a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover layer formed on an insulation substrate made of an organic film or a ceramic material, and through holes formed at positions corresponding to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package, with electrodes for connection to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package provided within through holes. In a method for mounting the capacitor, the capacitor is interposed between a flip-chip connected semiconductor element and a mounting substrate.

公开(公告)号：US06489613B1

公开(公告)日：2002-12-03

申请号：US09387878

申请日：1999-09-01

Applicant: Toru Mori ,  Katsuya Kawano

Inventor： Toru Mori ,  Katsuya Kawano

IPC: H01L3109

CPC classification number: H01L37/00 ,  G01J5/20 ,  H01L21/02565 ,  H01L21/02581

Abstract: An oxide thin film for bolometer having a vanadium oxide represented by VOx, where x satisfies 1.5≦x≦2.0, part of vanadium ion in the vanadium oxide being substituted by metal ion M, where the metal ion M is at least one of chromium (Cr), aluminum (Al), iron (Fe), manganese (Mn), niobium (Nb), tantalum (Ta) and titanium (Ti). Also, provided is an infrared detector having a bolometer thin film defined above. The oxide thin film for bolometer offers a low resistivity and a large TCR value. Also, the infrared detector offers a finer temperature resolution capability (NETD) as low as 0.03° C.

Abstract translation: 一种用于具有由VOx表示的氧化钒的测辐射热计的氧化物薄膜，其中x满足1.5 <= x <= 2.0，氧化钒中的钒离子的一部分被金属离子M取代，其中金属离子M是 铬（Cr），铝（Al），铁（Fe），锰（Mn），铌（Nb），钽（Ta）和钛（Ti）。 而且，提供了一种具有上述定影仪薄膜的红外检测器。 测辐射热计的氧化物薄膜具有低电阻率和较大的TCR值。 此外，红外检测器可提供低至0.03°C的更精细的温度分辨能力（NETD）。

公开(公告)号：US5633215A

公开(公告)日：1997-05-27

申请号：US601586

申请日：1996-02-14

Applicant: Toru Mori

Inventor： Toru Mori

IPC: C04B35/00 ,  C04B35/49 ,  C04B35/495 ,  C04B35/499 ,  H01B3/12 ,  H01G4/12 ,  C04B35/46 ,  C04B35/472

CPC classification number: C04B35/495 ,  C04B35/499

Abstract: A dielectric porcelain composition includes lead magnesium tungstate (Pb(Mg.sub.1/2 W.sub.1/2)O.sub.3), lead titanate (PbTiO.sub.3) and lead zirconate (PbZrO.sub.3) as main components at composition ratios of x, y and z respectively, wherein a point (x, y, z) in a ternary system is positioned on or within a boundary which comprises four straight line segments defined by four points of (0.725, 0.25, 0.025), (0.45, 0.525, 0.025), (0.30, 0.30, 0.40) and (0.475, 0.125, 0.40) in said ternary system as illustrated in FIG. 1, and wherein said main components are added with at least one rare earth oxide at a molar ratio in the range of 0.1-5.0 mol %.

Abstract translation: 电介质陶瓷组合物包括钨酸铅镁（Pb（Mg + E，fra 1/2 + EE W + E，fra 1/2 + EE）O 3），钛酸铅（PbTiO 3）和锆酸铅（PbZrO 3） 分别为x，y和z的组成比，其中三元系统中的点（x，y，z）位于包含由（0.725,0.25,0.025）的四个点定义的四个直线段的边界上或内部， （0.45,0.525,0.025），（0.30,0.30,0.40）和（0.475,0.125,0.40），如图3所示。 1，其中所述主要组分以0.1-5.0摩尔％的摩尔比加入至少一种稀土氧化物。