- 专利标题： Apparatus for reducing soft errors in dynamic circuits
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申请号： US10064921申请日： 2002-08-29
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公开(公告)号： US06794901B2公开(公告)日： 2004-09-21
- 发明人: Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
- 申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
- 主分类号： H03K19096
- IPC分类号： H03K19096
摘要：
An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.
公开/授权文献
- US20040041590A1 Apparatus for reducing soft errors in dynamic circuits 公开/授权日：2004-03-04
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