公开(公告)号：US09569402B2

公开(公告)日：2017-02-14

申请号：US13452078

申请日：2012-04-20

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

IPC分类号： G06F15/76 ,  G06F15/78 ,  H01L25/065

CPC分类号： G06F15/7867 ,  H01L25/0657 ,  H01L2924/0002 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2924/00

摘要： Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

摘要翻译： 提供三维（3-D）处理器结构，其通过以堆叠配置连接处理器构成。 例如，处理器系统包括包括第一处理器的第一处理器芯片和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于选择性地将第一和第二处理器芯片的第一和第二处理器配置为以多种操作模式中的一种操作，其中处理器可以被选择性地配置为独立地操作以聚合资源， 共享资源和/或组合以形成单个处理器映像。

公开(公告)号：US09471535B2

公开(公告)日：2016-10-18

申请号：US13452113

申请日：2012-04-20

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F15/173 ,  G06F9/38

CPC分类号： G06F15/17387 ,  G06F9/3802

摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

摘要翻译： 提供三维（3-D）处理器设备，其通过以堆叠配置连接处理器而构成。 例如，处理器系统包括第一处理器芯片，其包括第一处理器和包括第二处理器的第二处理器芯片。 第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。 处理器系统还包括模式控制电路，用于以多种操作模式之一选择性地操作处理器系统。 例如，在一种操作模式中，第一处理器和第二处理器被配置为实现超前功能，其中第一处理器操作主要执行线程，并且第二处理器操作预先执行的线程。

公开(公告)号：US09442884B2

公开(公告)日：2016-09-13

申请号：US13601289

申请日：2012-08-31

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F15/173 ,  G06F9/38

CPC分类号： G06F15/17387 ,  G06F9/3802

摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

公开(公告)号：US08826073B2

公开(公告)日：2014-09-02

申请号：US13602777

申请日：2012-09-04

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

IPC分类号： G06F11/00

CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

摘要翻译： 三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。 第一处理器芯片包括具有第一组状态寄存器的第一处理器。 第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。 第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。 模式控制电路以多种操作模式之一操作处理器系统。 在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器 第二处理器来检查第一处理器的状态。

公开(公告)号：US20130283008A1

公开(公告)日：2013-10-24

申请号：US13452078

申请日：2012-04-20

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

IPC分类号： G06F9/02

CPC分类号： G06F15/7867 ,  H01L25/0657 ,  H01L2924/0002 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2924/00

摘要： Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

公开(公告)号：US08521999B2

公开(公告)日：2013-08-27

申请号：US12721933

申请日：2010-03-11

申请人： Philip G. Emma ,  Allan M. Hartstein ,  Brian R. Prasky ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

发明人： Philip G. Emma ,  Allan M. Hartstein ,  Brian R. Prasky ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3846 ,  G06F9/3848

摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.

摘要翻译： 一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符 响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

公开(公告)号：US08141020B2

公开(公告)日：2012-03-20

申请号：US12493599

申请日：2009-06-29

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.

摘要翻译： 在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。 对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。 如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。 对于每个含设备的层中的所有相邻的功能块对，重复此例程。 随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。 该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

公开(公告)号：US20110286190A1

公开(公告)日：2011-11-24

申请号：US12774223

申请日：2010-05-20

申请人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

发明人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

IPC分类号： H05K7/02

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。 该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。 主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成 元件具有相对于主体层和芯片的平滑表面。

公开(公告)号：US07483325B2

公开(公告)日：2009-01-27

申请号：US11688455

申请日：2007-03-20

申请人： Philip G. Emma ,  William Roehr

发明人： Philip G. Emma ,  William Roehr

IPC分类号： G11C7/00

CPC分类号： G06F11/1064 ,  H03M13/03

摘要： Methods, systems, and apparatuses are provided for operating a cache comprising dynamic storage having an array of cells. At a refresh interval, the array of cells of the cache is refreshed. A determination is made whether an error is found in the cache at the refresh interval. If no error is found in the cache, the refresh interval is repeatedly increased by a predetermined amount until an error is found. If an error is found, the error is recovered from. A determination is made if a number of line deletions for the cache is a maximum number of line deletions for the cache. If the maximum number of line deletions is not attained, a line having the error is deleted, and the number of line deletions for the cache is increased. If the maximum number of line deletions for the cache is attained, the refresh interval is decreased by the predetermined amount.

摘要翻译： 提供了用于操作包括具有单元阵列的动态存储器的高速缓存的方法，系统和装置。 在刷新间隔时，缓存的单元阵列被刷新。 确定在刷新间隔在高速缓存中是否发现错误。 如果在高速缓存中没有发现错误，则重新增加刷新间隔预定的量，直到找到错误。 如果发现错误，则从中恢复错误。 如果缓存的行删除数量是缓存的行删除的最大数量，则确定。 如果没有达到最大行删除次数，则删除具有该错误的行，并且增加用于高速缓存的行删除次数。 如果达到高速缓存的行删除的最大数量，则刷新间隔减少预定量。

公开(公告)号：US20080235555A1

公开(公告)日：2008-09-25

申请号：US11688455

申请日：2007-03-20

申请人： Philip G. Emma ,  William Roehr

发明人： Philip G. Emma ,  William Roehr

IPC分类号： H03M13/00

CPC分类号： G06F11/1064 ,  H03M13/03

摘要： Methods, systems, and apparatuses are provided for operating a cache comprising dynamic storage having an array of cells. At a refresh interval, the array of cells of the cache is refreshed. A determination is made whether an error is found in the cache at the refresh interval. If no error is found in the cache, the refresh interval is repeatedly increased by a predetermined amount until an error is found. If an error is found, the error is recovered from. A determination is made if a number of line deletions for the cache is a maximum number of line deletions for the cache. If the maximum number of line deletions is not attained, a line having the error is deleted, and the number of line deletions for the cache is increased. If the maximum number of line deletions for the cache is attained, the refresh interval is decreased by the predetermined amount.

摘要翻译： 提供了用于操作包括具有单元阵列的动态存储器的高速缓存的方法，系统和装置。 在刷新间隔时，缓存的单元阵列被刷新。 确定在刷新间隔在高速缓存中是否发现错误。 如果在高速缓存中没有发现错误，则重新增加刷新间隔预定的量，直到找到错误。 如果发现错误，则从中恢复错误。 如果缓存的行删除数量是缓存的行删除的最大数量，则确定。 如果没有达到最大行删除次数，则删除具有该错误的行，并且增加用于高速缓存的行删除次数。 如果达到高速缓存的行删除的最大数量，则刷新间隔减少预定量。