发明授权
- 专利标题: Semiconductor memory device
- 专利标题(中): 半导体存储器件
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申请号: US10355079申请日: 2003-01-31
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公开(公告)号: US06795328B2公开(公告)日: 2004-09-21
- 发明人: Yoshiharu Kato , Kazufumi Komura , Satoru Kawamoto
- 申请人: Yoshiharu Kato , Kazufumi Komura , Satoru Kawamoto
- 优先权: JP2002-156144 20020529
- 主分类号: G11C506
- IPC分类号: G11C506
摘要:
A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.
公开/授权文献
- US20030223261A1 Semiconductor memory device 公开/授权日:2003-12-04
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