公开(公告)号：US07675801B2

公开(公告)日：2010-03-09

申请号：US12273269

申请日：2008-11-18

申请人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

发明人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4068

摘要： A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

摘要翻译： 用于半导体存储器件的刷新方法具有高抗噪性，较低的功耗和较低的成本。 在自刷新模式中未被选择的一个或多个存储单元块的所有字线被控制为具有基本上处于地平面的浮动电位。 即使当字线和位线短路时，该控制也可以防止可能由噪声引起的存储单元信息的破坏，并且还防止漏电流的产生。 不需要用于防止产生泄漏电流的保险丝等，从而实现较低的成本。

公开(公告)号：US07492232B2

公开(公告)日：2009-02-17

申请号：US11802637

申请日：2007-05-24

申请人： Yasushige Ogawa ,  Satoru Kawamoto

发明人： Yasushige Ogawa ,  Satoru Kawamoto

IPC分类号： H03B1/00 ,  H03B5/00 ,  H03B5/24

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

摘要翻译： 提供了一种振荡器电路，其能够通过在振荡开始时避免可能发生在操作/停止控制可行型振荡器电路的频率不稳定的输出而获得稳定的频率。 在这种振荡电路中，振荡允许信号（EN）将振荡器部分置于振荡可操作状态，由此控制器部分开始工作。 已经看到其操作的控制器部分将振荡频率控制信号（VR）改变成对应于预定振荡频率的信号值，以便在振荡器部分设置振荡频率。 此外，振荡器部分响应于在检测器部分将输入的信号与预定信号值进行比较之后输出的检测信号（MON）输出振荡信号，并检测输入信号达到预定信号值。 由此，可以检测振荡频率控制信号（VR）的瞬态。 也就是说，可以避免由于瞬态振荡频率控制信号（VR）引起的不稳定振荡​​信号的输出。

公开(公告)号：US07245549B2

公开(公告)日：2007-07-17

申请号：US11058302

申请日：2005-02-16

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

摘要翻译： 提供一种半导体存储装置及其控制方法，其可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线容量分量，通过更高的电压电平来驱动均衡电容分量较高的布线的电路。

公开(公告)号：US07239210B2

公开(公告)日：2007-07-03

申请号：US11372146

申请日：2006-03-10

申请人： Yasushige Ogawa ,  Satoru Kawamoto

发明人： Yasushige Ogawa ,  Satoru Kawamoto

IPC分类号： H03B5/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

摘要翻译： 提供了一种振荡器电路，其能够通过在振荡开始时避免可能发生在操作/停止控制可行型振荡器电路的频率不稳定的输出而获得稳定的频率。 在这种振荡电路中，振荡允许信号（EN）将振荡器部分置于振荡可操作状态，由此控制器部分开始工作。 已经观察其操作的控制器部分将振荡频率控制信号（VR）改变成对应于预定振荡频率的信号值，以便在振荡器部分设置振荡频率。 此外，振荡器部分响应于在检测器部分将输入的信号与预定信号值进行比较之后输出的检测信号（MON）输出振荡信号，并检测输入信号达到预定信号值。 由此，可以检测振荡频率控制信号（VR）的瞬态。 也就是说，可以避免由于瞬态振荡频率控制信号（VR）引起的不稳定振荡​​信号的输出。

公开(公告)号：US20070120249A1

公开(公告)日：2007-05-31

申请号：US11602230

申请日：2006-11-21

申请人： Satoru Kawamoto

发明人： Satoru Kawamoto

IPC分类号： H01L23/14

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/029 ,  Y10T428/24917 ,  H01L2924/00

摘要： A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.

摘要翻译： 电路基板包括多个电介质构件和多个布线图案。 多个布线图案通过多个电介质构件彼此堆叠。 多个电介质构件包括安装电介质构件。 多个布线图案的第一布线图案设置在安装电介质构件的一侧。 多个布线图案的第二布线图案设置在安装电介质构件的相对侧上。 第一长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的相对侧之间的长度。 第二长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的一侧之间的长度。 第一长度小于第二长度。

公开(公告)号：US07142468B2

公开(公告)日：2006-11-28

申请号：US10299713

申请日：2002-11-20

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4085 ,  G11C2207/2281

摘要： It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0 is deactivated with appropriate timing that is between time after bit line pairs (BL0 and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time τA for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time τB of a sense amplifier and equalizing time τC of the bit line pairs. Thereby, pre-charge period can be shortened.

摘要翻译： 旨在提供一种半导体存储器件和半导体存储器件的控制方法，其能够缩短在连续的数据存取操作结束后即连续的数据读/写操作而导致的预充电操作时间，而不会导致恢复的恶化 对存储单元的电压和初始数据存取时间的延迟。 激活字线WL 0被禁用，其中位置线对（BL 0和/ BL 0，... BLN和/ BLN）之间的时间之间的适当定时被差分放大到全幅度电压电平，并且列选择线 CL 0，。 。 。 选择CLN。 也就是说，字线的去激活时间τA可以嵌入在连续数据访问操作的时段中。 可以在时间内终止预充电操作，该时间是读出放大器的去激活时间τB和位线对的均衡时间tauC之和。 从而可以缩短预充电期间。

公开(公告)号：US20060250167A1

公开(公告)日：2006-11-09

申请号：US11482129

申请日：2006-07-07

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

公开(公告)号：US20060209583A1

公开(公告)日：2006-09-21

申请号：US11341029

申请日：2006-01-27

申请人： Shozo Kawabata ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

发明人： Shozo Kawabata ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

公开(公告)号：US06956777B2

公开(公告)日：2005-10-18

申请号：US10299775

申请日：2002-11-20

申请人： Kazufumi Komura ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C11/403 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/783 ,  G11C11/406 ,  G11C2207/2227

摘要： There are intended to provide a semiconductor memory device capable of data access with higher speed and improvement of data transfer rate by shortening refresh operation cycle by stable low-current-consumption operation, and a control method of such a semiconductor memory device. In advance to the refresh operation mode signal M(I), control signal SW is outputted. Consequently, the switching sections select stored address bus Ladd from each storing section and stored-redundancy-judgment-result bus LJ and output address information subject to refresh operation to a word-line-driving-system circuit. After the address information from each storing section is outputted, a control signal LCH is outputted. As a result, an address switching section selects refresh address bys Add(I) subject to next refresh operation and each storing section stores address Add(I) fetched in an internal address bus IAdd and its redundancy judgment result RJ(I).

摘要翻译： 旨在通过稳定的低电流消耗操作来缩短刷新操作周期，以及这种半导体存储器件的控制方法，提供能够以更高速度进行数据访问并提高数据传输速率的半导体存储器件。 提前到刷新操作模式信号M（I），输出控制信号SW。 因此，切换部分从存储部分选择存储的地址总线Ladd和存储的冗余判断结果总线LJ以及进行刷新操作的输出地址信息到字线驱动系统电路。 在输出来自每个存储部分的地址信息之后，输出控制信号LCH。 结果，地址切换部分选择通过下一次刷新操作的添加（I）的刷新地址，并且每个存储部分存储在内部地址总线IAdd中获取的地址Add（I）及其冗余判断结果RJ（I）。

公开(公告)号：US06802721B2

公开(公告)日：2004-10-12

申请号：US10351368

申请日：2003-01-27

申请人： Kazuya Sanada ,  Toshiaki Yagura ,  Satoru Kawamoto ,  Akihiro Yanagisawa

发明人： Kazuya Sanada ,  Toshiaki Yagura ,  Satoru Kawamoto ,  Akihiro Yanagisawa

IPC分类号： H01R1200

CPC分类号： H05K5/0069 ,  H01R12/62 ,  H05K1/147

摘要： An electronic device includes a circuit board, a flexible printed wiring board, and an electric connector. The circuit board includes an electronic circuit. The flexible printed wiring board is electrically connected to the electronic circuit. The electric connector includes a plurality of leads and a connector body. Each lead has a substantially straight end and a bent end. A surface of the connector body is substantially parallel to a surface of the flexible printed wiring board. Each bent end of the leads is located on the surface of the connector body to be substantially parallel to the surface of the flexible printed wiring board. The connector is electrically connected to the flexible printed wiring board using the leads. With the structure of the connector, the circuit board and the electric connector is relatively readily connected by the flexible printed wiring board in the manufacturing process of the electronic device.

摘要翻译： 电子设备包括电路板，柔性印刷线路板和电连接器。 电路板包括电子电路。 柔性印刷线路板电连接到电子电路。 电连接器包括多个引线和连接器本体。 每个引线具有基本上直的端部和弯曲端部。 连接器主体的表面基本上平行于柔性印刷线路板的表面。 引线的每个弯曲端位于连接器主体的表面上，以基本上平行于柔性印刷线路板的表面。 连接器使用引线电连接到柔性印刷线路板。 利用连接器的结构，在电子设备的制造过程中，电路板和电连接器通过柔性印刷线路板相对容易地连接。