发明授权
- 专利标题: Semiconductor etch speed modification
- 专利标题(中): 半导体蚀刻速度修改
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申请号: US10611837申请日: 2003-06-30
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公开(公告)号: US06806204B1公开(公告)日: 2004-10-19
- 发明人: Jun-Fei Zheng , Jesper Hanberg
- 申请人: Jun-Fei Zheng , Jesper Hanberg
- 主分类号: H01L21302
- IPC分类号: H01L21302
摘要:
In accordance with embodiments of the methods of the present invention, a sacrificial layer provides an etch speed modification to effectively etch multiple semiconductor devices having dissimilar materials to a common layer or substrate with a common etch process. The time to etch remove a second exposed portion is compared with the time to etch remove a first exposed portion, and a sacrificial layer is deposited on the first exposed portion having a time to etch remove substantially equal to the difference. The sacrificial layer is provided to have predetermined material composition, material property and layer thickness, among other things, to provide a desired time to etch remove. The methods also provide for self-aligned via formation providing highly defined vias by the etch removal of sacrificial material rather than direct etching of the vie. The methods also provide planarization between two or more devices.
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