Invention Grant
- Patent Title: Testing apparatus embedded in scribe line and a method thereof
- Patent Title (中): 嵌入划线中的测试装置及其方法
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Application No.: US10151028Application Date: 2002-05-21
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Publication No.: US06809541B2Publication Date: 2004-10-26
- Inventor: Lin-Kai Bu , Kun-Cheng Hung
- Applicant: Lin-Kai Bu , Kun-Cheng Hung
- Priority: TW90112307A 20010522
- Main IPC: G01R3126
- IPC: G01R3126

Abstract:
A testing method and a testing a voltages apparatus embedded in the scribe line on a wafer are disclosed, for testing the to be measured from a die on a wafer. The testing apparatus includes a multiplexer and a comparator. The multiplexer receives the voltages to be measured and outputs a multiplexing or selected voltage according to a selection signal. The comparator receives a reference voltage and the multiplexing voltage and then outputs a digital result by comparing the reference voltage, and the multiplexing voltage. The digital result can be applied to a digital testing machine, such that testing speed is increased and testing cost is decreased. Moreover, the testing apparatus embedded in the scribe lines has the capability to compensate for the comparator's offset, and accordingly, the testing reliability is also improved.
Public/Granted literature
- US20020175696A1 Testing apparatus embedded in scribe line and a method thereof Public/Granted day:2002-11-28
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